Solid State Imaging Device Gate Isolation via Sidewall Spacers
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Solution Overview
Problem
The existing solid state imaging devices face issues with inter-gate leakage current and potential differences due to uneven dielectric capacitance between gate electrodes, leading to reduced saturated charge transfer efficiency and breakdown voltage.
Innovation Solution
The formation of sidewall spacers using CVD insulating films in the overhang portions of the first gate electrodes modifies the overhang shape, preventing etching residue and ensuring equal nitride film thickness under both gate electrodes, thus electrically isolating them effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal oxidation is used to form silicon oxide film on gate electrodes, then the oxide film provides electrical separation, but non-uniform thickness results in increased inter-gate leakage current
Solution Approach 1:
The patent applies preliminary action by forming the nitride film to a specific thickness before thermal oxidation, and using etch stop layers to pre-determine the oxidation depth. This ensures that even though oxidation occurs non-uniformly, the final oxide thickness remains controlled and uniform by stopping the oxidation process at the nitride film interface.
Solution Approach 2:
The nitride film serves as an intermediary layer between the oxide film and the gate electrode. It acts as an etch stop layer that prevents excessive oxidation and ensures uniform oxide thickness by providing a clear interface where oxidation stops, thereby mediating the non-uniform oxidation process.
2Ease of manufacture
If etching is used to pattern polysilicon layers for gate electrodes, then gate structures are formed, but film thickness reduction occurs leading to potential differences between gates
Solution Approach 1:
The patent introduces nitride films as intermediary etch stop layers during the patterning process. These nitride films prevent excessive etching of the polysilicon gate electrodes, ensuring that all gates maintain uniform thickness even when patterned at different stages, thereby eliminating potential differences between gates.
Solution Approach 2:
The patent applies preliminary action by forming nitride etch stop layers before polysilicon deposition and patterning. This preliminary structure ensures that subsequent etching processes do not remove excessive polysilicon material, maintaining uniform gate thickness across all electrodes.
3Reliability
If sidewall spacers are formed to modify overhang portions, then electrical isolation is improved, but device structure complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the isolation structure into multiple functional layers: oxide films for primary insulation, nitride films for etch stopping, and sidewall spacers for geometric control. This segmented approach improves isolation reliability while keeping each layer's function simple and well-defined.
Solution Approach 2:
The sidewall spacers act as intermediary structures that modify the overhang portions of the gate electrodes. By introducing these spacer layers, the patent achieves better electrical isolation and controls the geometry of the gate structures without requiring complete redesign of the entire transfer portion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces inter-gate leakage current, maintains excellent saturated charge transfer efficiency, and enhances breakdown voltage by ensuring uniform potential distribution across the gate electrodes.
Implementation Method 1
The formation of sidewall spacers using CVD insulating films in the overhang portions of the first gate electrodes modifies the overhang shape
Implementation Method 2
each of the second gate electrodes is separated from an associated one of the first gate electrodes by the second oxide film, the sidewall spacer and the second nitride film
Data Source
AI summary
A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).