Impedance Calibration Circuit for Semiconductor Memory
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Solution Overview
Problem
The increase in I/O speed of semiconductor memory is limited, leading to impedance mismatch between output drivers in physical and test electrode areas, which hampers the sharing of direct access balls for signal input/output in memory systems.
Innovation Solution
An impedance calibration circuit that includes a first replica driver group and a second replica driver group, along with an impedance calibration unit, performs independent impedance matching operations to prevent impedance mismatch between the output drivers in the physical and test electrode areas, using a reference resistance setting unit and multiplexing sections to calibrate resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If I/O speed is increased to improve operation speed, then bandwidth is improved, but impedance mismatch occurs between output drivers in physical and test electrode areas
Solution Approach 1:
The patent divides the impedance calibration function into separate replica driver groups: a first replica driver group for the physical area and a second replica driver group for the test electrode area. Each group independently calibrates impedance for its respective area, preventing cross-interference and ensuring reliable impedance matching at high I/O speeds.
Solution Approach 2:
The patent applies local calibration by configuring replica drivers specifically for each area (physical area and test electrode area) with independent impedance calibration units. This allows each region to have optimized impedance characteristics tailored to its specific electrical characteristics, maintaining reliability despite high-speed operation.
2Productivity
If multiple semiconductor memories share a signal line to increase bandwidth, then productivity is improved, but impedance mismatch prevents successful signal input/output
Solution Approach 1:
The patent segments the calibration function into area-specific replica driver groups, with the first group handling physical area calibration and the second group handling test electrode area calibration. This segmentation ensures that each area's impedance is independently optimized, enabling multiple memories to share signal lines without mutual interference.
Solution Approach 2:
The patent changes impedance parameters through independent calibration units that adjust the electrical characteristics of each replica driver group. By dynamically adjusting impedance parameters for each area, the system enables multiple semiconductor memories to share signal lines while maintaining signal integrity and preventing mismatch.
Data Source
AI summary
An embodiment may include a first replica driver group configured for replicating an output driver of a physical area. A second replica driver group configured for replicating an output driver of a test electrode area for direct access of a memory, and an impedance calibration unit configured to independently perform an impedance matching operation of the first replica driver group and the second replica driver group.