Impedance Calibration Circuit with Comparator Offset Compensation
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Solution Overview
Problem
As memory device operating speeds increase, signal swing widths decrease, making signals more susceptible to distortion due to impedance mismatches caused by PVT variations, and conventional impedance calibration methods are inefficient in compensating for comparator random offsets and achieving precise impedance matching between pull-up and pull-down circuits.
Innovation Solution
An impedance calibration circuit with multiple variable impedance circuits, comparators, and control circuits that perform simultaneous and sequential calibration operations to adjust impedances, using switch circuits to connect inputs and outputs in various configurations, thereby efficiently canceling comparator random offsets and achieving precise impedance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional impedance calibration methods are used, then the calibration operation can be performed, but the comparator random offsets cannot be efficiently compensated and precise impedance matching between pull-up and pull-down circuits cannot be achieved
Solution Approach 1:
The patent combines the pull-up circuit calibration and pull-down circuit calibration into a single unified calibration operation. By using one comparator to sequentially compare voltages from both pull-up and pull-down circuits against a reference voltage, the system achieves coordinated impedance matching for both circuits simultaneously, eliminating the random offset errors that would otherwise affect each circuit independently.
Solution Approach 2:
The patent implements a feedback mechanism where the comparator output is used to control variable resistors in both pull-up and pull-down circuits. The comparator continuously compares the voltages and provides feedback signals to adjust the resistors until the voltages match the reference voltage, thereby achieving precise impedance matching while compensating for comparator random offsets through the coordinated adjustment of both circuits.
2Measurement precision
If multiple separate calibration operations are performed for pull-up and pull-down circuits, then each circuit can be calibrated individually, but the locking time increases and the structure becomes more complex
Solution Approach 1:
The patent merges multiple separate calibration operations into a single unified calibration process. One comparator is used to sequentially compare voltages from both pull-up and pull-down circuits against a reference voltage, and a single control signal coordinates the adjustment of variable resistors in both circuits. This unified approach achieves the same calibration accuracy as separate operations but reduces the total locking time by eliminating redundant comparison and adjustment cycles.
Data Source
AI summary
An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.