Impedance Control Circuit for Stable I/O Driver Calibration
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Solution Overview
Problem
Conventional semiconductor circuits face challenges in maintaining consistent impedance of data input/output drivers due to variations in process, voltage, or temperature, leading to abnormal impedance control signals, especially during auto-refresh operations affected by power noise.
Innovation Solution
An impedance control signal generation circuit with a control unit that determines whether generated impedance control signals are within a predetermined range, using reference signals from initial auto-calibration, and generates an update enable signal to prohibit updates when signals are abnormal, ensuring only normal impedance control signals are used to calibrate the data input/output driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If impedance control signals are updated during auto-refresh operations, then the impedance calibration can adapt to PTV variations, but power noise causes abnormal impedance control signals to be generated
Solution Approach 1:
The patent performs initial auto-calibration during system initialization to establish baseline impedance control signals before normal operation begins. This preliminary calibration creates a reference state that prevents subsequent power noise during auto-refresh operations from causing abnormal signal updates, as the impedance is already optimized from the initial calibration.
Solution Approach 2:
The patent implements a feedback mechanism where the control unit continuously monitors impedance control signals generated during auto-refresh operations. When abnormal signals are detected (indicating power noise interference), the feedback loop prevents these abnormal signals from being latched and applied to the input/output driver, thereby maintaining signal reliability while still allowing normal calibration updates to proceed.
2Stability of the object's composition
If impedance control signals are constantly updated, then the impedance can be maintained according to PTV variations, but abnormal signals from power noise will corrupt the calibration
Solution Approach 1:
The control unit monitors each generated impedance control signal to determine whether it falls within a predetermined normal range. This feedback mechanism allows the system to maintain impedance consistency by applying only valid calibration signals while rejecting abnormal signals caused by power noise, thus preserving both stability and reliability.
Solution Approach 2:
The patent introduces an intermediary control unit and prohibition unit between the impedance control signal generation unit and the storage unit. This intermediary layer filters out abnormal signals before they can corrupt the calibration process, allowing constant updates to proceed safely by blocking only the harmful abnormal signals while permitting normal calibration signals to pass through.
3Productivity
If the storage unit latches impedance control signals whenever update pulse signals are generated, then calibration updates occur frequently, but abnormal signals are also latched causing impedance deviations
Solution Approach 1:
The control unit provides feedback to the prohibition unit about the quality of each generated impedance control signal. This feedback enables the system to maintain high calibration update frequency by allowing normal signals to be latched while simultaneously ensuring impedance precision by blocking abnormal signals from being latched, thus resolving the contradiction between productivity and precision.
Solution Approach 2:
The prohibition unit acts as an intermediary gate between the storage unit and the update pulse signals. It receives update pulse signals and selectively permits or blocks them based on the quality assessment of the corresponding impedance control signals. This intermediary mechanism maintains high update frequency by allowing normal updates while preserving precision by blocking abnormal updates.
Data Source
AI summary
An impedance control signal generation circuit includes an impedance control signal generation unit configured to generate an impedance control signal in response to a command, a storage unit configured to latch and output the impedance control signal in response to an update pulse signal, a control unit configured to determine whether the impedance control signal is within a predetermined range and generate an update enable signal according to a determination result, and a prohibition unit configured to control input of the update pulse signal to the storage unit in response to the update enable signal.