Logic Circuit Coupling Arrangements TRIZ Cases

A controlled-impedance clock loop and crossed output routing cut timing skew in current steering DACs, improving SFDR at multi-GHz frequencies.

Dynamic impedance switching cuts line-noise amplitude in slew-rate serial outputs, preserving stable high levels and preventing communication errors.

Independent pull-up and pull-down impedance control cuts I/O power use while preserving signal integrity on transmission lines.

Selectable parallel resistors and on-die sensing keep memory bus termination impedance matched despite process, voltage, and temperature shifts.

Selectable capacitors balance calibration-path loading in an output driver to stabilize slew rate while maintaining impedance calibration.

A controller equalizes node voltages to tune Rx termination resistance accurately even when the termination voltage differs from the power rail.

Switchable low- and high-impedance input paths let one receiver handle NGS, LVDS, PODL, DRSL, and SSTL with lower power.

Digital on-die impedance tuning measures polysilicon resistance and compensates temperature and voltage drift to reduce memory bus reflections.

Two parallel resistive loads use adjacent control codes to average on-die termination impedance, improving signal integrity with less decoder area.

Pre-emphasis circuits boost high-frequency transitions in a voltage-mode line driver to cut attenuation, inter-symbol interference, and power use.

Switchable multi-level on-die termination improves memory bus impedance matching, cutting reflections, attenuation, and bit errors.

Switchable high-load and low-load memory terminations balance reflection suppression and signal attenuation to improve signaling margins.

Blocks abnormal impedance updates during auto-refresh so semiconductor I/O drivers stay calibrated despite process, voltage, temperature, and power noise.

An internal calibration clock shortens resistance code trimming cycles, cutting calibration time and power use in semiconductor ICs.

Keeping ODT on briefly after data reception suppresses power-supply noise on bidirectional signal lines and preserves transmission accuracy.

Periodic switching enables memory termination only during data transitions, cutting power use while preserving impedance matching and signal quality.

Cooperative on-die termination splits signaling current across memory devices to cut switching noise, simplify control, and support faster links.

Keeping ODT active for a short period after data reception reduces power-supply noise on bidirectional memory lines and preserves transfer accuracy.

Stacked MOS transistors let chip output drivers meet transmission line impedance while limiting electrostatic discharge damage.

Clustered on-package I/O reuses one configurable physical layer to deliver high bandwidth while cutting power, area, and latency.

When line noise disrupts slew-rate-controlled outputs, dynamic impedance switching stabilizes drive voltage and preserves serial communication.

Adaptive scaling and reference-based thresholds let a semiconductor switch driver handle varied logic levels with better noise immunity.

Multiple switchable on-die terminations match line impedance, absorb reflections, and protect signaling margins in high-speed memory links.

On-chip feedback senses output pad capacitance and tunes driver strength within one cycle to keep slew rate stable across wide load variation.

A bias-controlled HDMI termination circuit adds adjustable resistance only when needed to cut signal reflection and support longer high-speed cables.

An auxiliary driver adds transition-only pre-emphasis to keep voltage swing consistent and reduce jitter from ISI across output frequencies.

Using only npn transistors, this circuit converts single-phase shutdown input into differential control to simplify manufacturing and widen use.

Only one chip on a shared I/O channel performs termination, improving impedance matching and reducing signal distortion in high-speed memory packages.

Keeping ODT on briefly after data reception suppresses power-supply noise and protects bidirectional memory signal accuracy.

A two-stage buffer control scheme disables data input buffers outside write periods, cutting unnecessary memory module power use.

Multiple on-die termination resistors let each memory bank select impedance for better channel matching and more efficient data transfer.

Shared on-die calibration pads and replica termination circuits enable precise multi-mode impedance matching with less IC area.

Continuous feedback recalibrates on-die termination resistance against PVT variation, reducing data distortion and abnormal operation.

Multiple reference voltage units use distributed termination voltages to improve signal detection accuracy and reduce data errors.

Adjustable impedance damps ringing in inductive high-speed links, improving data accuracy while limiting signal attenuation.

Selectable on-die termination resistors let memory banks use decoded impedance values, improving signal transfer across changing bank configurations.

A timed pull-up transistor boosts open-drain bus rise time while limiting capacitive loading and avoiding crowbar current in programmable I/O.

Code-modified calibration lets one termination impedance unit deliver multiple settings, cutting pad capacitance and signal distortion.

Dynamic on-die termination adjusts memory data bus impedance against process, voltage, and temperature shifts to cut reflections and protect timing margins.

Clock-code comparison enables DDR3 dynamic ODT with burst-length timing, improving impedance matching under aging and temperature shifts.

A voltage-dividing stage and buffer help LTPS level shifters handle low input voltage and high threshold variation with fewer delays and errors.

Frequency-based ODT pipeline switching preserves command latency and time margin across wider memory clock ranges.

Internal positive feedback boosts weak differential swings in ECL-to-CMOS translation, raising gain while cutting delay in high-speed circuits.