Open-Drain Output Driver With Timed Pull-Up for Faster Bus Rise Time
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Solution Overview
Problem
Programmable logic devices, such as FPGAs and CPLDs, face challenges in driving high-speed open-drain bus interfaces due to excessive output capacitance, which affects rise time and performance, especially at frequencies above 1 GHz, as they need to accommodate multiple output standards with additional circuitry that increases capacitance.
Innovation Solution
The implementation of an output driver with a tri-state controller that activates a pull-up transistor for a short duration during the transition from logic 'Low' to 'High' to reduce capacitive loading, using a configuration where the first transistor couples the bus line to a reference voltage and the second transistor couples it to a supply voltage, with internal and external resistors optimized to minimize RC time constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple output standards are accommodated with dedicated circuitry in I/O blocks, then programming flexibility and application versatility are improved, but output capacitance increases making high-speed driving difficult
Solution Approach 1:
The patent extracts the pull-up resistor function from the I/O block circuitry and places it externally, connected to the output pad through a capacitor. This removal eliminates the capacitive contribution of internal pull-up resistors and other I/O circuitry, significantly reducing output capacitance while maintaining the ability to support multiple output standards through reconfiguration of the remaining circuit elements.
Solution Approach 2:
The patent introduces a capacitor as an intermediary element between the output pad and the external pull-up resistor. This capacitor isolates the output pad from the resistive loading effects during high-speed transitions while still allowing the external pull-up to function properly, effectively mediating between the low-capacitance requirement and the need for external termination.
2Speed
If output capacitance is reduced by removing internal circuitry, then rise time performance is improved, but ability to accommodate multiple output standards is reduced
Solution Approach 1:
The patent employs dynamic control of the output driver circuitry through reconfiguration capabilities that allow the same physical circuit to be dynamically adjusted for different output standards. The output pad can be reconfigured to support various standards (LVCMOS, LVTTL, HSTL, SSTL, GTL, PCI, LVDS, etc.) while maintaining low capacitance by selectively enabling/disabling circuit elements and adjusting termination configurations based on the required standard.
3Quantity of substance
If external pull-up resistor is used with capacitor coupling, then capacitive loading is minimized, but circuit complexity increases
Solution Approach 1:
The patent creates a universal output driver architecture where the same basic circuit structure with external pull-up resistor and capacitor coupling can serve multiple output standards and applications. The reconfiguration capabilities allow this single design to universally support different voltage levels, impedance requirements, and timing characteristics, reducing the need for multiple specialized circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the rise time performance of the bus line, reducing settling time and improving the ability to drive high-speed open-drain buses by minimizing capacitive loading and avoiding crowbar current issues, thus achieving better performance compared to prior art solutions.
Implementation Method 1
a first driving device that has a first terminal coupled to a bus line terminal... The first driving device is configured to couple the bus line terminal to a first supply potential when activated by a first control signal
Implementation Method 2
a second driving device that has a first terminal coupled to the bus line terminal... the second driving device is configured to couple the bus line to a second supply potential when the second driving device is activated by a second control signal
Implementation Method 3
The implementation of an output driver with a tri-state controller that activates a pull-up transistor for a short duration during the transition from logic 'Low' to 'High' to reduce capacitive loading
Data Source
AI summary
In one embodiment, an output driver is disclosed. The output driver has a first driving device (Q1) that has a first terminal coupled to a bus line terminal, and a second driving device (Q2) that has a first terminal coupled to the bus line terminal. The first driving device (Q1) is configured to couple the bus line terminal to a reference voltage when activated by a first control signal, and the second driving device (Q2) is configured to couple the bus line terminal to a first supply voltage (Vcc) when the second driving device (Q2) is activated by a second control signal. The output driver also has a controller configured to activate the second control signal after the first control signal is deactivated. The second control signal remains active for a first fixed period of time.