Memory ODT Resistor Selection for Channel Impedance Matching
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Solution Overview
Problem
Existing semiconductor memory devices face inefficiencies in signal transfer due to a fixed impedance of a single ODT resistor, which fails to optimize channel impedance regardless of the number of memory banks allocated, leading to suboptimal data transfer efficiency.
Innovation Solution
The implementation of multiple on-die termination (ODT) resistors, each allocated independently to memory banks or modules, allows for adjustable impedance selection based on a combination of chip selection, ODT control, and code control signals, optimizing channel impedance during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single fixed impedance ODT resistor is used, then device complexity is reduced, but data transfer efficiency deteriorates due to inability to optimize channel impedance for different memory bank configurations
Solution Approach 1:
The single ODT resistor is segmented into multiple ODT resistors (first ODT resistor and second ODT resistor) with different impedance values. Each resistor is selectively connected to the data pad through switching elements (first and second switching elements) controlled by selection signals. This allows the system to choose appropriate impedance values based on the number of memory banks allocated, thereby optimizing data transfer efficiency without requiring a completely complex reconfiguration system.
Solution Approach 2:
The ODT resistor configuration is made dynamic through the use of switching elements that can selectively connect different impedance values to the data pad. The selection of which ODT resistor to use is controlled by selection signals generated from decoded address signals and ODT control signals. This dynamic reconfiguration capability allows the impedance to be adapted to different operating conditions (different numbers of memory banks) while maintaining a relatively simple overall structure.
2Adaptability or versatility
If multiple ODT resistors with different impedances are implemented, then adaptability to different memory bank configurations is improved, but device complexity increases
Solution Approach 1:
The ODT control structure is segmented into functional modules: a decoder that receives address signals and ODT control signals, switching elements that are independently controlled by selection signals, and multiple ODT resistors with different impedance values. This modular segmentation allows each component to perform a specific function, making the overall complex system manageable and maintainable while achieving high adaptability.
Solution Approach 2:
The decoder pre-processes the address signals and ODT control signals to generate the appropriate selection signals before they reach the switching elements. This preliminary action ensures that the correct ODT resistor is selected in advance based on the memory bank configuration, allowing the switching elements to simply execute the pre-determined selection without requiring complex real-time decision logic, thus reducing control structure complexity.
Data Source
AI summary
A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.