Memory Module Buffer Control for Low-Power Data Input Buffers
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing unnecessary power consumption by data input buffers, particularly due to the difficulty in designing buffer control circuits that efficiently disable data input buffers during non-operational periods, especially as semiconductor chips are miniaturized and multiple memory devices are integrated on a single chip.
Innovation Solution
A buffer control circuit is designed with a first control signal generator that generates an internal buffer control signal based on write latency and internal control signals, and a second control signal generator that generates a buffer control signal based on this internal signal and a termination control signal, enabling or disabling data input buffers and termination units to match impedance and reduce power consumption during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data input buffer is enabled to receive external input data through the I/O pad, then the data input buffer can perform its function, but current consumption rises abruptly
Solution Approach 1:
The patent applies dynamics by making the data input buffer's operational state changeable between enabled and disabled states based on real-time operational needs. The buffer control circuit dynamically adjusts the buffer's state according to whether a write operation is currently being performed, allowing the system to optimize power consumption while maintaining data input functionality when required.
2Speed
If the buffer control circuit is disposed close to the data input buffer to rapidly execute control operation, then control speed is improved, but routing the termination control signal from the control signal generator becomes more difficult as chips are miniaturized
Solution Approach 1:
The patent applies segmentation by dividing the control signal generation into two independent parts: the buffer control signal generated locally by the buffer control circuit near the data input buffer, and the termination control signal generated separately by the control signal generator. This segmentation allows each control path to be optimized independently, enabling fast local control while simplifying signal routing for termination control.
Solution Approach 2:
The patent introduces an intermediary approach by using the termination control signal as a mediating control input to the buffer control circuit. Instead of requiring direct complex routing from the control signal generator to the buffer control circuit, the termination control signal serves as an intermediary that works in conjunction with the locally generated buffer control signal to achieve the desired buffer control functionality.
3Device complexity
If the buffer control circuit generates the buffer control signal based on the control signal DOFFB1, then the control signal can be generated, but the data input buffer operates during periods when it need not be driven, causing unnecessary power consumption
Solution Approach 1:
The patent applies feedback by using the termination control signal as a feedback input to the buffer control circuit. The termination control signal provides information about the current operational state (whether a read operation is in progress) back to the buffer control circuit, enabling it to adjust the buffer control signal accordingly. This feedback mechanism ensures the data input buffer is disabled during periods when it is not needed, eliminating unnecessary power consumption.
Data Source
AI summary
A buffer control circuit, a semiconductor memory device for a memory module including the buffer control circuit, and a control method of the buffer control circuit, in which power consumption can be reduced. The buffer control circuit includes a first control signal generator that generates an internal buffer control signal in response to write latency signals and internal control signals, and a second control signal generator that generates a buffer control signal in response to the internal buffer control signal and a termination control signal. It is therefore possible to reduce unnecessary power consumption incurred by a data input buffer.