Positive-Feedback Translator Circuit for Fast ECL-to-CMOS Conversion
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Solution Overview
Problem
Conventional ECL-to-CMOS translator circuits trade off speed and gain, resulting in significant delay and bottlenecks in high-speed applications, especially as transistor sizes decrease and logic output differential swings are reduced.
Innovation Solution
Incorporating positive feedback loops within the translator circuit, specifically through internal feedback transistors, to dynamically boost signal gain and minimize phase delay, allowing for simultaneous increase in both gain and speed without compromising bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional translator designs are used to translate ECL signals to CMOS signals, then voltage translation is achieved, but speed and gain are traded off resulting in significant delay
Solution Approach 1:
The patent applies positive feedback by introducing feedback transistors (Q1, Q2) that feed a portion of the output signal back to the input stage. This positive feedback mechanism amplifies the signal swing and accelerates the switching transitions, thereby increasing translator speed while minimizing delay. The feedback transistors dynamically adjust the gain during the transition period, resolving the speed-delay tradeoff inherent in conventional translator designs.
2Speed
If transistor size is reduced to achieve faster transmission rates, then transmission speed increases, but logic output differential swings are reduced
Solution Approach 1:
The patent introduces intermediary feedback transistors (Q1, Q2) that act as mediators between the input differential stage and the output stage. These feedback transistors amplify the weakened differential swings from smaller transistors by feeding back a portion of the stronger output signal, thereby restoring the signal strength while maintaining the high-speed benefits of smaller transistor dimensions.
3Power
If conventional translator circuits are used for high gain voltage translations, then voltage translation is achieved, but bandwidth is compromised due to speed-gain tradeoff
Solution Approach 1:
The patent implements dynamic gain control through positive feedback where the feedback transistors (Q1, Q2) dynamically adjust their conduction state based on the instantaneous signal level. During transitions, the feedback provides high gain to amplify small differential signals, while during steady states, the feedback automatically reduces to maintain bandwidth. This dynamic behavior resolves the static tradeoff between gain and bandwidth in conventional translators.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables translator circuits to achieve high gain voltage translations with minimal phase delay, exemplified by >2 Gbps operation and >10 gain with <500 psec delay, even at high temperatures, effectively addressing the speed and gain limitations of conventional designs.
Implementation Method 1
The switching circuit include a first positive feedback loop including a first internal feedback transistor that reinforces a signal level at the first control node and a second positive feedback loop including a second internal feedback transistor that reinforces a signal level at the second control node
Data Source
AI summary
An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132). The switching circuit (130) include a first positive feedback loop including a first internal feedback transistor (MN1) that reinforces a signal level at the first control node (131) and a second positive feedback loop including a second internal feedback transistor (MN2) that reinforces a signal level at the second control node 132. An output stage (140) has at least one input coupled to receive at least one output signal from the switching circuit (130) and provide at least one translated output supplying the higher logic-level voltage range signal.