Semiconductor Memory ODT Decoding for Bank-Specific Impedance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face inefficiencies in signal transfer due to the use of a single fixed impedance ODT resistor, which fails to optimize channel impedance regardless of the number of memory banks, leading to suboptimal data transfer efficiency.
Innovation Solution
The implementation of multiple on-die termination (ODT) resistors, each allocated to a memory bank or module, allows for independent impedance control during read/write operations through a code channel, termination resistor decoder, and ODT block, enabling selection of appropriate impedance values based on decoded signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single fixed impedance ODT resistor is used, then the device complexity is reduced, but the channel impedance optimization capability deteriorates
Solution Approach 1:
The patent divides the single ODT resistor into multiple ODT resistors (first ODT resistor and second ODT resistor) with different impedance values. Each ODT resistor is selectively connected to the data pad based on the number of memory banks, allowing independent optimization for different configurations without increasing overall device complexity.
Solution Approach 2:
The patent implements dynamic selection of ODT resistors based on the operational conditions (number of memory banks). The system can switch between different ODT resistors using control logic that monitors bank configuration, enabling adaptive impedance optimization rather than a fixed single-resistor approach.
2Adaptability or versatility
If multiple ODT resistors are implemented for each memory bank, then the channel impedance optimization is improved, but the device complexity increases
Solution Approach 1:
The patent applies different impedance values to different ODT resistors based on local requirements of memory bank configurations. Each ODT resistor is optimized for specific bank scenarios (single bank, dual bank, etc.), providing localized impedance optimization without requiring a completely separate control system for each resistor.
Solution Approach 2:
The patent creates a universal ODT control mechanism that handles multiple memory bank configurations using a single control logic structure. The termination resistor decoder and control circuitry serve multiple functions by interpreting bank configuration signals and selecting appropriate ODT resistors, reducing overall control complexity despite having multiple resistors.
3Manufacturing precision
If a fixed impedance ODT resistor is used, then the manufacturing precision requirements are reduced, but the data transfer efficiency deteriorates
Solution Approach 1:
The patent changes the impedance parameter of the ODT resistor based on operational conditions. By providing multiple ODT resistors with different impedance values and selectively activating them according to memory bank configuration, the system optimizes data transfer efficiency for each scenario without requiring extremely tight manufacturing tolerances on a single fixed resistor value.
Data Source
AI summary
A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.