Programmable Impedance Memory Barrier Layers Vacuum Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming programmable impedance cells in integrated circuit devices often result in uncontrolled reaction products due to ambient air exposure, leading to inadequate or unpredictable programmable resistance responses and incorporation of active metal layers into ion conductor layers.
Innovation Solution
The formation of memory device structures with a programmable impedance layer is achieved by creating a substantially planar structure using a first and second barrier layer to prevent undesirable element propagation, and forming memory layers and conductive barrier layers under controlled conditions such as vacuum environments, temperature variations, and electrical biases to ensure reliable and predictable impedance variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If active metal layer is formed in the presence of ambient air, then the formation process is simple and fast, but uncontrolled reaction products are created leading to inadequate or unpredictable programmable resistance responses
Solution Approach 1:
The patent applies inert atmosphere by forming the active metal layer in a vacuum environment rather than ambient air. This prevents uncontrolled reactions between the active metal and atmospheric components (water vapor, oxygen), eliminating unpredictable reaction products while maintaining formation speed through efficient vacuum deposition processes.
2Ease of manufacture
If active metal layer is formed in ambient air, then the process is easier to implement, but reaction products affect the incorporation of active metal into ion conductor layers in an uncontrolled manner
Solution Approach 1:
The patent implements vacuum environment formation to prevent uncontrolled reactions between active metal and ambient air components. This ensures clean interfaces and controlled incorporation of active metal into ion conductor layers, achieving precise manufacturing outcomes while maintaining process efficiency through standardized vacuum deposition techniques.
3Device complexity
If barrier layers are not used, then the structure is simpler, but undesirable elements can propagate and affect memory layer performance
Solution Approach 1:
The patent extracts and isolates potentially harmful elements by introducing barrier layers between the active metal layer and ion conductor layers. These barrier layers selectively block undesirable elements and reaction products from propagating into the memory layers, protecting memory performance while maintaining overall structural efficiency.
Solution Approach 2:
The barrier layers create a protective environment that prevents harmful interactions between layers. By forming these barriers in a vacuum environment, the patent ensures clean interfaces and prevents contamination, thereby protecting the memory layers from degradation while maintaining structural simplicity through targeted barrier placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more reliable and uniform memory structures with improved programmable impedance responses, preventing uncontrolled reactions and ensuring thinner, more predictable layer thicknesses, which enhances the integration and performance of memory devices within integrated circuits.
Implementation Method 1
forming an active metal layer under a vacuum
Implementation Method 2
forming memory layers and conductive barrier layers under controlled conditions such as vacuum environments, temperature variations, and electrical biases
Data Source
AI summary
A programmable impedance memory device structure can include a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface, including a memory material layer in contact with the planar surface, the first barrier layer being formed above a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface. The first and second barrier layers can have lower mobility rates for at least one element within the memory material layer than the first insulating layer, and the memory material layer can be programmable by application of an electrical field between at least two different impedance states.