IMS Memory Encoding for Dense Parallel Match Detection
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Solution Overview
Problem
Conventional ternary content addressable memory (TCAM) technologies face challenges in power consumption and on/off ratio, making it difficult to distinguish all-match cases from one-bit mismatches during data comparisons, and suffer from low storage density, inadequate for large data searches.
Innovation Solution
A memory device with an in-memory search (IMS) array and encoding method that programs every 2N adjacent memory units to represent 2N-bits of encoded data, using threshold voltages to enhance storage density and enable efficient parallel data comparisons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional TCAM memory types (SRAM, 2T2R RRAM, FeRAM) are used for parallel-search operations, then the memory can perform parallel data comparisons, but the power consumption is high and the on/off ratio is insufficient to distinguish all-match from one-bit mismatch cases
Solution Approach 1:
The patent changes the operating parameters of the memory cells by introducing multiple threshold voltage levels (first threshold voltage and second threshold voltage) that are distinct from the search signal voltage levels. This allows the memory cells to store encoded data with higher precision and enable better distinction between match and mismatch cases, thereby improving the on/off ratio without significantly increasing power consumption during parallel search operations.
2Device complexity
If conventional TCAM memory is used for data storage, then the memory structure is simple, but the storage content density is low and insufficient for searching large amounts of data
Solution Approach 1:
The patent merges multiple memory cells (specifically 2N adjacent memory units) into a single functional memory cell that stores encoded data representing M bits of original data, where M = 2(N-1). This merging approach increases the storage content density by allowing N memory units to work together as one logical unit, enabling the memory to store more data per physical cell while maintaining relatively simple individual cell structures.
Solution Approach 2:
The patent changes the data representation parameter by encoding M bits of original data into 2N bits of encoded data with specific threshold voltage assignments. This encoding scheme allows the memory to achieve higher storage density by representing the same amount of information with fewer physical memory units, effectively increasing the storage content density without proportionally increasing device complexity.
3Quantity of substance
If more memory units are used to increase storage density, then the storage content density improves, but the difficulty of detecting and measuring match accuracy increases
Solution Approach 1:
The patent segments the detection task by dividing the memory array into rows where each row contains memory units that can be independently controlled and sensed. The first driving circuit controls the word lines to select specific rows, and the sensing circuit senses the match signal lines for each row independently. This segmentation allows the system to detect match accuracy row-by-row, making the overall detection process manageable despite the increased storage density achieved through the 2N-to-1 encoding scheme.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The encoding method improves storage density and enables effective parallel data searches with reduced power consumption, distinguishing between all-match and mismatch cases.
Implementation Method 1
the 2N memory units in the memory cell are programmed to have a first threshold voltage or a second threshold voltage to represent an encoded data of 2N-bits
Data Source
AI summary
An encoding method is provided for a memory device which includes an in-memory search (IMS) array having several memory units. The memory units in a same horizontal row are coupled to a first driving circuit through corresponding word lines and coupled to a sensing circuit through a match signal line. Every 2N adjacent memory units in the same horizontal row are arranged as a memory cell. An original data of M-bits is encoded to an encoded data of 2N-bits with a first encoded area including the first to N-th bits of the encoded data and a second encoded area including the (N+1)-th to 2N-th bits of the encoded data. The M bits of the original data have an equivalent binary value increased by an incremental step which is P times of an incremental step for the N bits of the first encoded area.