In-DRAM ECC Mechanism for DDR4 Memory Channel Overhead Reduction
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Solution Overview
Problem
Current DDR4 techniques face challenges in maintaining reliability, availability, and serviceability (RAS) due to increased system ECC overhead and chipkill requirements, which are exacerbated by the decrease in data width and the need for additional ECC overhead with increased memory channels per DIMM.
Innovation Solution
A new DDR interface that utilizes in-DRAM ECC for error correction, allowing the DRAM to correct certain types of memory errors internally and direct the memory controller for assistance with other errors, thereby reducing ECC overhead and enhancing RAS capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DDR4 interface uses increased memory channels per DIMM to increase bandwidth, then data transfer capability is improved, but ECC overhead and system complexity increase
Solution Approach 1:
The patent divides the error correction function into two segments: in-DRAM ECC handling for single-bit errors and memory controller ECC handling for multiple-bit errors. This segmentation allows each component to specialize in specific error types, reducing the burden on the memory controller and lowering overall system ECC overhead despite increased memory channels.
Solution Approach 2:
The patent extracts the single-bit error correction capability from the memory controller and places it directly in the DRAM chips themselves. By taking out this function to the DRAM level, the memory controller is freed from handling all error correction tasks, reducing its complexity and the overall system ECC overhead.
2Adaptability or versatility
If DDR4 interface decreases data width to maintain compatibility, then backward compatibility is improved, but RAS (Reliability, Availability, Serviceability) deteriorates
Solution Approach 1:
The patent segments error correction responsibilities based on error severity: in-DRAM ECC handles single-bit errors (maintaining RAS for common errors), while memory controller ECC handles multiple-bit errors (providing enhanced protection). This segmentation allows the system to maintain backward compatibility with narrower data widths while improving RAS capabilities through distributed error correction.
Solution Approach 2:
The patent implements in-DRAM ECC as a preemptive measure that corrects single-bit errors before they propagate to the memory controller. This beforehand cushioning protects against common errors at the source, improving RAS without requiring the memory controller to handle all error cases, thus maintaining compatibility with reduced data widths.
3Device complexity
If single ECC chip per memory channel is used to reduce overhead, then ECC overhead is reduced, but error correction capability for multiple errors is compromised
Solution Approach 1:
The patent segments error correction by location and severity: in-DRAM ECC chips handle single-bit errors locally within each memory channel, while the memory controller's ECC system handles multiple-bit errors across the channel. This segmentation allows a single ECC chip per memory channel to suffice, reducing overhead while maintaining comprehensive error correction capability through the collaborative effort of both in-DRAM and controller-level ECC.
Data Source
AI summary
A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.