In-Memory Computation Circuit for Low-Area Partial Sum Generation
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Solution Overview
Problem
Existing memory arrays do not efficiently perform in-memory computations, leading to larger area and higher power consumption in operations such as those required for convolutional neural networks.
Innovation Solution
Incorporating memory arrays with integrated selection circuits, accumulators, and adder trees that perform mathematical operations directly on stored data, enabling in-memory computation to generate partial sums using smaller areas and lower power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data bits are moved between memory arrays and computation circuits, then computations can be performed, but area and power consumption increase
Solution Approach 1:
The patent combines memory storage elements and computation logic into a single integrated memory structure. Weight data is stored directly in the memory array, and computation operations are performed by controlling current flow through selected memory cells during read operations, eliminating the need for separate computation circuits and data movement pathways.
Solution Approach 2:
The memory array serves multiple functions: storing weight data, performing computation operations, and generating results. The same memory infrastructure used for data storage is also utilized for mathematical computations through controlled read operations, reducing the need for dedicated computation hardware.
2Productivity
If data bits are moved between memory arrays and computation circuits, then computations can be performed, but power consumption increases
Solution Approach 1:
The patent combines memory storage elements and computation logic into a single integrated memory structure. Weight data is stored directly in the memory array, and computation operations are performed by controlling current flow through selected memory cells during read operations, eliminating the need for separate computation circuits and data movement pathways.
Solution Approach 2:
The memory array performs computation operations using its own stored weight data without requiring external computation circuits. The computation is achieved by controlling read operations to sum currents from selected memory cells, allowing the memory system to serve its own computation needs and eliminate power-consuming data movement.
3Adaptability or versatility
If multiple layers of operations are performed with data movement, then complex computations can be achieved, but area and power increase
Solution Approach 1:
The patent performs computation operations through sequential read phases where different sets of memory cells are accessed in alternating patterns. Weight data is read in multiple passes with different selection patterns, accumulating results through controlled current summation across phases, enabling complex computations without additional hardware.
Data Source
AI summary
A memory circuit includes a plurality of columns, each column including a plurality of storage elements and a plurality of multipliers, wherein each multiplier is coupled to a corresponding storage element, a data register configured to store a plurality of input data elements, and a plurality of multiplexers coupled to the data register. Each multiplexer is configured to output a bit of a plurality of bits of a corresponding input data element of the plurality of input data elements to a corresponding multiplier of the plurality of multipliers of each column, and each multiplier of the plurality of multipliers of each column is configured to output a product data element based on a weight data element stored in the corresponding storage element and the bit of the plurality of bits of the corresponding input data element.