In-Memory Computing Circuit Error Mitigation via Data Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In-memory computing architectures for neural networks face errors due to poor memory storage and computing inefficiencies, affecting the accuracy of data processing in applications like image recognition and data analysis.
Innovation Solution
A data processing circuit and fault-mitigating method that combines Von Neumann architecture with in-memory computing, dividing sequence data into sub-sequences for partial processing by a computing unit and memory, improving error rates by allocating specific operations to each architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If in-memory computing architecture is used to improve processing efficiency and reduce power consumption, then processing speed and energy efficiency are improved, but error rate increases due to poor memory yield and unstable cell resistance
Solution Approach 1:
The patent divides sequence data into multiple sub-sequences and processes them through different paths: some sub-sequences are processed entirely in-memory, while others are processed partially in-memory and partially in a computing unit. This segmentation allows the system to maintain high processing efficiency for in-memory operations while reducing overall error rates by offloading critical computations to more reliable external computing units.
Solution Approach 2:
The patent introduces a computing unit as an intermediary between the memory and the final output. This computing unit receives sub-sequences from the memory, performs MAC operations on them, and returns results to be combined with in-memory computation results. This intermediary layer acts as a buffer that reduces the propagation of errors from unstable memory cells while maintaining the speed benefits of in-memory computing.
2Productivity
If all MAC operations are performed in-memory to maximize processing efficiency, then productivity is improved, but manufacturing precision deteriorates due to poor memory yield and hardware defects
Solution Approach 1:
The patent segments the computational workload by dividing sequence data into sub-sequences and assigning different processing strategies to different sub-sequences. Some sub-sequences undergo complete in-memory processing for speed, while others undergo partial in-memory processing followed by correction in external computing units, thereby balancing manufacturing precision with productivity.
Solution Approach 2:
The patent dynamically adjusts the processing parameters by varying the degree of in-memory computation applied to different sub-sequences. Based on error rates and computational requirements, the system can change the proportion of operations performed in-memory versus in external computing units, optimizing both manufacturing precision and productivity for different data sets and workloads.
3Speed
If sequence data is processed entirely in-memory, then processing speed is improved, but data correctness deteriorates due to output errors from unstable cell resistance and non-ideal current sensing
Solution Approach 1:
The patent segments the data processing pipeline into in-memory computation stages and external verification stages. By dividing sequence data into sub-sequences and processing them through multiple paths with different levels of verification, the system maintains high processing speed for straightforward operations while ensuring data correctness through external validation of critical results.
Solution Approach 2:
The patent implements a feedback mechanism where the computing unit processes sub-sequences and returns correction information to the memory system. This feedback loop allows the system to identify and correct errors that occur during in-memory computation, thereby maintaining data correctness without significantly compromising processing speed, as the feedback is integrated into the overall processing flow rather than being a separate post-processing step.
Data Source
AI summary
A data processing circuit and a fault-mitigating method are provided. In the method, multiple sub-sequences are divided from sequence data. A first sub-sequence of the sub-sequences is accessed from a memory for a multiply-accumulate (MAC) operation to obtain a first computed result. The MAC operation is performed on a second sub-sequence of the sub-sequences in the memory to obtain a second computed result. The first and the second computed results are combined, where the combined result of the first and the second computed results is related to the result of the MAC operation on the sequence data directly. Accordingly, the error rate could be reduced, so as to mitigate fault.