In-Memory Data Switching Network for Memory Array Processing

Solution Overview

Problem

Current memory systems face inefficiencies in processing performance and power consumption due to the need for external communication between processing resources and memory arrays, which can slow down operation cycles and increase energy use.

Innovation Solution

The implementation of an in-memory data switching network within a memory device, utilizing a shared I/O line and sensing circuitry to reorganize data within the memory array, allowing for faster data movement and processing without external processing resources, thereby reducing the time and power required for operation cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If data is accessed via external bus between processing resources and memory array, then device complexity is reduced, but processing speed decreases and power consumption increases

Engineering Contradiction:

Improvedevice complexityVSAvoidprocessing speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent combines processing resources with the memory array by integrating functional unit circuitry directly within the memory device. This merging eliminates the need for external buses and interfaces, allowing data to be processed in-place within the memory array, thereby improving processing speed while maintaining manageable device complexity through systematic integration.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an in-memory data switching network as an intermediary component within the memory device that enables efficient data routing between memory cells and functional units. This internal switching network acts as a mediator that facilitates fast data movement without requiring external bus interfaces, thus improving processing speed while keeping the overall device complexity controlled.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If data is accessed via external bus between processing resources and memory array, then ease of operation is improved, but power consumption increases

Engineering Contradiction:

Improveease of operationVSAvoidpower consumption

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent merges processing resources with the memory array by integrating functional unit circuitry directly within the memory device. This integration eliminates the need for external buses and interfaces, allowing data to be processed in-place within the memory array, thereby improving processing speed while maintaining manageable device complexity through systematic integration.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an in-memory data switching network as an intermediary component within the memory device that enables efficient data routing between memory cells and functional units. This internal switching network acts as a mediator that facilitates fast data movement without requiring external bus interfaces, thus improving processing speed while keeping the overall device complexity controlled.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Device complexity

If processing resources are implemented externally to memory array, then device complexity is reduced, but operation cycle time increases

Engineering Contradiction:

Improvedevice complexityVSAvoidoperation cycle time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent combines processing resources with the memory array by integrating functional unit circuitry directly within the memory device. This merging eliminates the need for external buses and interfaces, allowing data to be processed in-place within the memory array, thereby improving processing speed while maintaining manageable device complexity through systematic integration.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements an in-memory data switching network that pre-establishes data pathways and routing configurations within the memory device before processing operations begin. This preliminary setup of internal data routes allows for rapid data movement to functional units without the delays associated with external bus arbitration and protocol handshaking, thus reducing operation cycle time while keeping device complexity controlled.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11474965B2Apparatuses and methods for in-memory data switching networks

Publication Date: 2022.10.18 MICRON TECHNOLOGY INC

AI summary

The present disclosure includes apparatuses and methods for in-memory data switching networks. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array of memory cells. An input/output (I/O) line is shared as a data path for in-memory data switching associated with the array. An in-memory data switching network is selectably coupled to the respective shared I/O line. A controller is configured to couple to the in-memory data switching network and direct enablement of a switch protocol.