In-Memory Logic Circuit Using Bit-Line Sensing for Low-Transfer Computing
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Solution Overview
Problem
Existing data storage systems with separate memory and calculation circuits face high energy consumption and reduced performance due to extensive data transfer between these components, particularly in systems that require parallel calculations.
Innovation Solution
A data storage circuit incorporating a non-volatile memory matrix and a data processing circuit that performs elementary logical operations within the storage circuit itself, eliminating the need for data transfer outside the circuit. This circuit is compatible with ferroelectric, resistive, or mixed memory types and includes a logical treatment circuit with an amplifier, comparator, and control unit to manage reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data transfer between separate memory circuits and computation circuits is performed, then data storage and processing can be achieved, but energy consumption increases significantly and computing performance decreases
Solution Approach 1:
The patent merges memory storage and computation functions into a single integrated circuit. Memory cells are directly connected to logic processing circuits, allowing data to be processed in-place without transfer between separate components. This eliminates the energy-intensive data movement operations while maintaining both storage and computing capabilities within the same circuit structure.
2Adaptability or versatility
If additional transistors are added to each memory cell to enable logic processing, then computation capability is improved, but circuit area and manufacturing complexity increase significantly
Solution Approach 1:
The patent makes existing memory cell components serve multiple functions. The same memory cell structure that stores data is also configured to participate in logic operations through selective activation. By using the inherent transistor and capacitor structures of the memory cells for both storage and computation, the design avoids adding dedicated computation transistors while still achieving logical processing capability.
3Ease of operation
If data is read from ferroelectric memory cells, then data can be processed, but the reading operation destroys the stored data
Solution Approach 1:
The patent performs a preliminary write operation immediately after reading data from ferroelectric memory cells. The read operation destroys the original data, but the system has already captured the necessary information for computation. Subsequently, the same or related data is rewritten back into the memory cells, restoring them for future operations. This preliminary capture followed by restoration ensures continuous operation without permanent data loss.
Data Source
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Figure 2b
AI summary
The invention relates to a data storage circuit comprising: - a memory cell matrix; - a logic processing circuit configured to perform a logic operation having as operands N binary data stored in N input memory cells with N≥2; the second input/output nodes of said input memory cells being connected by a common bit line; the logic processing circuit comprising: • a transimpedance amplifier stage configured to provide an analog read signal from the voltage of the common bit line; • a comparator for comparing the analog read signal to a first adjustable reference voltage to generate a digital output signal corresponding to the result of the logic operation; • a control unit configured to adjust the reference voltage to an amplitude chosen from N distinct predetermined amplitudes, according to the type of logic operation.