In-Memory Processor Register Indexing for More Compute Operations
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Solution Overview
Problem
The communication speed between memory devices and host devices in memory systems acts as a bottleneck, limiting the number of calculation operations that can be performed by in-memory processors due to constraints such as the width of the command/address signal channel.
Innovation Solution
An in-memory processor is designed with an instruction list circuit, calculation registers, a processing management circuit, and a calculation circuit to perform multiple calculation operations, and a control logic circuit to dynamically change register indexing rules based on commands from an external device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the in-memory processor uses a fixed register indexing rule, then the control logic is simple, but the number of calculation operations is limited due to communication bottlenecks
Solution Approach 1:
The patent implements dynamic register indexing rules where the register index is not fixed but determined by multiple factors including command type, bank address, and column address. The processing management circuit dynamically selects appropriate register indexes based on the current operation context, allowing the same instruction to operate on different registers for various calculation operations, thereby increasing productivity without excessive complexity
Solution Approach 2:
The patent segments the register indexing mechanism into multiple independent components: command type determination, bank address determination, column address determination, and register indexing rule selection. Each component handles a specific aspect of the indexing process, allowing complex register selection to be broken down into manageable segments that can be processed independently, reducing overall control logic complexity
2Productivity
If the command/address signal channel width is increased to allow more calculation operations, then more operations can be performed, but the device complexity and communication overhead increase
Solution Approach 1:
The patent makes the existing command/address signal channel multi-functional by encoding multiple pieces of information (command type, bank address, column address, register indexing rule) within the same signal structure. Instead of requiring separate dedicated channels for each function, the same channel carries composite information that enables multiple calculation operations through intelligent decoding and dynamic register indexing, increasing productivity without increasing physical channel width
Solution Approach 2:
The patent changes the parameter encoding within the command/address signals to include register indexing information derived from command type, bank address, and column address. By modifying how parameters are represented and interpreted in the existing signal channel, the system enables additional calculation operations without requiring wider physical channels, thus improving productivity while maintaining signal channel simplicity
Data Source
AI summary
According to some embodiments of the present disclosure, an in-memory processor included in a memory device may be provided. The in-memory processor may include an instruction list circuit configured to store a first instruction including a first register indexing field, a calculation register array including a plurality of calculation registers, a processing management circuit configured to store a register indexing rule table and an address log that includes a first register indexing rule that corresponds to a value of the first register indexing field, and the processing management circuit is configured to identify a first calculation register of the plurality of calculation registers based on the first register indexing rule and the address log, and a calculation circuit configured to perform a first calculation operation for the first instruction based on the first calculation register.