In-Memory Processing Semiconductor Device with Bit Line Connection
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Solution Overview
Problem
Conventional semiconductor devices for in-memory processing are limited to performing only AND and OR operations, requiring the addition of a large gate logic circuit, which restricts their applications.
Innovation Solution
A semiconductor device with a cell circuit comprising multiple memory arrays and a control circuit that allows for the connection of bit lines between sub-arrays using an array connecting circuit, enabling operations such as NOT and partial sum operations without the need for a large gate logic circuit, through the use of sense amplifiers and partial sum generating circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional in-memory processing operations are limited to AND and OR operations, then the device complexity remains low, but the adaptability and versatility of the memory device are restricted
Solution Approach 1:
The memory device performs computation operations using its own memory cells and sense amplifiers without requiring external gate logic circuits. The in-memory processing capability allows the memory device to serve both as storage and computation unit, eliminating the need for additional processing circuitry and achieving versatility without increased device complexity
Solution Approach 2:
The memory device is designed to perform multiple operations including AND, OR, NOT, and partial sum operations using the same memory array and sense amplifier infrastructure. This multi-functionality is achieved through different operation modes of the existing components rather than adding dedicated circuits for each operation type
2Productivity
If data transfer between memory device and external chip is reduced by performing computation inside the memory device, then power consumption and processing time are reduced, but the device requires additional circuitry for in-memory processing
Solution Approach 1:
The memory device performs computation operations using its own memory cells and sense amplifiers without requiring external gate logic circuits. The in-memory processing capability allows the memory device to serve both as storage and computation unit, eliminating the need for additional processing circuitry and achieving versatility without increased device complexity
Solution Approach 2:
The computation function is merged with the storage function by utilizing the same memory array and sense amplifier infrastructure for both data storage and computation operations. This integration eliminates the need for separate processing circuits and achieves in-memory processing without increasing overall device complexity
Data Source
AI summary
A semiconductor device includes a cell circuit including a plurality of memory arrays, and a control circuit configured to control the cell circuit. A memory array of the plurality of memory arrays has a plurality of sub-arrays including a first sub-array and a second sub array, and an array connecting circuit configured to connect bit lines of the first sub-array to respective corresponding bit lines of the second sub-array according to a copy signal. The semiconductor device may further include a partial sum circuit configured to perform charge sharing between a plurality of bit lines of the first sub-array.