In-Package Memory Direct Testing Bypassing Cache Circuitry
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Solution Overview
Problem
Existing methods for testing in-package memory devices often face challenges such as timing delays and protocol incompatibilities due to the involvement of cache circuitry and standardized interfaces, which can introduce uncertainties and inefficiencies during testing operations.
Innovation Solution
A memory subsystem that bypasses cache-related features and uses direct access methods to facilitate in-order command operations with deterministic latency, employing protocol translation and timing adjustments to ensure accurate testing of memory dies within the package without relying on cache or other subsystem features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If cache circuitry and standardized interfaces are used for testing in-package memory, then the memory can be accessed through normal operational pathways, but timing delays and protocol incompatibilities are introduced
Solution Approach 1:
The patent segments the testing pathway by introducing a dedicated test interface that operates independently from the cache circuitry and standardized host interface. This allows test commands to reach the memory die directly without passing through cache control logic or protocol translation layers, thereby eliminating timing delays while maintaining ease of operation through a specialized access path.
Solution Approach 2:
The patent introduces a test interface as an intermediary component between the test equipment and the memory die. This intermediary provides direct electrical connections to the memory die, bypassing the cache and standardized interface, thus acting as a mediator that enables fast, deterministic access for testing purposes without affecting normal operational pathways.
2Adaptability or versatility
If cache circuitry is involved in testing operations, then normal memory access protocols can be used, but protocol incompatibilities and uncertainties are introduced
Solution Approach 1:
The patent segments the access pathways by creating a dedicated test interface that is physically and functionally separate from the cache circuitry and standardized host interface. This segmentation allows test operations to proceed through a direct, controlled path to the memory die, eliminating protocol translation requirements and ensuring reliable, deterministic access without compromising the adaptability of the standardized interface for normal operations.
Solution Approach 2:
The patent extracts the testing function from the standardized interface and cache circuitry by providing a separate, dedicated test interface. This extraction removes the source of protocol incompatibilities and uncertainties, allowing testing to proceed with direct, deterministic access to the memory die while the standardized interface remains available for normal operational use.
3Productivity
If direct access to memory die is implemented, then testing speed and accuracy improve, but additional test interfaces and connections are required
Solution Approach 1:
The patent applies universality by designing the test interface to share physical infrastructure with the memory die packaging, such as utilizing existing substrate real estate, redistribution layers, and packaging processes. The test interface is integrated into the same package structure, allowing it to function as an additional access point without requiring entirely separate hardware infrastructure, thus improving productivity while minimizing the increase in device complexity.
Solution Approach 2:
The patent merges the test interface with the existing memory package structure, combining testing functionality with the standard packaging infrastructure. By integrating the test interface into the same package substrate and utilizing shared physical resources, the patent achieves direct access for improved testing efficiency while avoiding the need for completely separate, additional contacts or packaging structures.
Data Source
AI summary
Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.