In Situ Thin-Film Capacitors for Low-Inductance Package Decoupling
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Solution Overview
Problem
Existing decoupling capacitors, such as MLCCs and on-die MIM capacitors, fail to provide sufficient capacitance close to the die due to high inductance and high ESR, leading to voltage droop issues in advanced processing platforms, and ex situ TFCs are costly and limit design flexibility.
Innovation Solution
In situ thin film capacitors (TFCs) are integrated into the package substrate using standard packaging fabrication processes, allowing for customizable placement and reduced ESR, providing decoupling capacitance closer to the die with lower inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multilayer ceramic capacitors are used for decoupling, then capacitance is provided, but high inductance path and packaging limitations prevent effective high-frequency performance
Solution Approach 1:
The patent transitions from three-dimensional discrete component packaging (MLCCs) to a planar two-dimensional capacitor structure integrated directly into the package substrate. This dimensional change eliminates the need for vertical stacking and complex packaging, thereby reducing inductance while maintaining capacitance functionality.
Solution Approach 2:
The capacitor structure is merged with the package substrate itself, integrating the decoupling function directly into the substrate rather than using separate discrete components. This merging eliminates additional inductance from component leads and packaging, providing effective high-frequency decoupling.
2Reliability
If on-die MIM capacitors are added to meet capacitance demand, then decoupling capacitance increases, but equivalent series resistance becomes excessively high and effectiveness is lost at high frequencies
Solution Approach 1:
The patent moves the capacitor implementation from the die level (where ESR is high) to the package substrate level, utilizing the substrate's inherent lower resistance characteristics. This spatial relocation to another dimension of the system architecture reduces ESR while maintaining the required decoupling capacitance.
Solution Approach 2:
The patent changes the physical parameters of the capacitor implementation by using the package substrate's material properties and geometry rather than on-die MIM structures. This parameter change includes utilizing the substrate's lower resistance and optimized trace routing to achieve lower ESR.
3Reliability
If ex situ fabricated decoupling TFC sheets are embedded into the package substrate, then decoupling capacitance is provided, but manufacturing cost increases and design flexibility is limited
Solution Approach 1:
The capacitor fabrication process is merged with the existing package substrate manufacturing process. The TFC structure is formed using the same semiconductor fabrication techniques already employed for the substrate, eliminating the need for separate ex situ capacitor fabrication and assembly steps, thereby reducing manufacturing cost.
Solution Approach 2:
The package substrate manufacturing process itself provides the decoupling capacitance function through integrated TFC formation. Rather than requiring external capacitor components to be separately fabricated and assembled, the substrate fabrication process automatically creates the necessary capacitive structures, making the system self-sufficient.
4Reliability
If ex situ fabricated decoupling TFC sheets are used, then decoupling capacitance is provided, but design flexibility is limited compared to in situ fabrication
Solution Approach 1:
The capacitor design is merged with the substrate design process, allowing simultaneous optimization of both the substrate layout and capacitor placement. This integration enables design flexibility as the capacitor structures can be positioned and sized according to specific electrical requirements rather than being limited to standard discrete component footprints.
Solution Approach 2:
The patent enables local optimization of decoupling capacitance by forming TFC structures at specific locations within the package substrate where they are most needed. This local quality approach allows design flexibility to place capacitors close to specific die attachments or high-frequency signal paths rather than using uniform discrete component placement.
Data Source
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AI summary
Embodiments described herein are directed to a thin film capacitor (TFC) for power delivery that is in situ in a package substrate and techniques of fabricating the TFC. In one example, the TFC includes a first electrode, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. Each of the dielectric layer and the second electrode comprises an opening. Furthermore, the two openings are positioned over one another such that the openings expose a surface of the first electrode. In this example, a first vertical interconnect access (via) is positioned on the exposed surface of the first electrode and a second via is positioned on an exposed surface of the second electrode. The TFC can be positioned in or on a layer of the package substrate close to a component (e.g., a die, a die stack, etc.) on the package substrate that may require a decoupling capacitance.