Inactive Fin Layout for Tighter GAA FET Active Spacing
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Solution Overview
Problem
In advanced semiconductor technology nodes, layout restrictions on active area spacing and semiconductor fin spacing are constrained by inactive fin structures, limiting the scaling of field-effect transistors such as planar FETs, FinFETs, and gate-all-around (GAA) devices.
Innovation Solution
The inactive fin structures are formed only between the source/drain epitaxial features, allowing active fin structures and overlying gate structures to be free of these constraints, thereby improving active area spacing without the need for inactive fin structures between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If inactive fin structures are formed between active fin structures, then layout restrictions on active area spacing are constrained, but manufacturing precision and fabrication process window are improved
Solution Approach 1:
The patent removes inactive fin structures from between active fin structures, extracting only the necessary inactive fins at the edges. This eliminates the spacing constraints that inactive fins imposed on active fin structures, allowing tighter spacing between active fins while maintaining manufacturing precision through selective placement of inactive fins only where needed for process control.
Solution Approach 2:
The patent applies inactive fin structures selectively - forming them at the edges between active fin structures and epitaxial regions where they are needed for process control, while deliberately omitting them from between active fin structures where they would constrain spacing. This local differentiation resolves the contradiction by providing manufacturing precision where required without limiting active fin spacing where flexibility is needed.
2Reliability
If inactive fin structures are formed between active fin structures, then electrical bridging risks are reduced, but active area spacing is limited
Solution Approach 1:
The patent extracts inactive fin structures only from the regions between active fin structures, removing the spacing limitations they imposed. Electrical bridging protection is maintained through alternative means such as proper isolation structures and selective inactive fin placement at edges, allowing reduced spacing between active fins while preserving reliability.
Solution Approach 2:
The patent provides differential protection against electrical bridging - using inactive fin structures at edge regions where they are most effective for process control, while relying on other isolation mechanisms between active fin structures. This allows tighter spacing between active fins without compromising reliability, as the inactive fins are strategically placed only where needed.
3Manufacturing precision
If inactive fin structures are formed between source/drain epitaxial features, then fabrication process window is improved, but device complexity increases
Solution Approach 1:
The patent removes unnecessary inactive fin structures from between active fin structures, reducing device complexity. Inactive fins are retained only at the essential locations between active fins and epitaxial regions, maintaining the fabrication process window benefits while eliminating redundant structures that increased complexity.
Solution Approach 2:
The patent applies inactive fin structures locally only where they provide maximum manufacturing benefit - at the interfaces between active fin structures and epitaxial regions. This selective placement maintains the fabrication process window improvement while minimizing device complexity by avoiding inactive fins in regions where they are not needed.
Data Source
AI summary
A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.