Inclined Sidewall Memory Strings for Reduced Gate Leakage
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Solution Overview
Problem
Conventional semiconductor storage devices face challenges in refining device dimensions due to cost and technological limitations, with EUV exposure devices being expensive, and existing manufacturing methods lead to gate leakage and data retention issues due to damage during Reactive Ion Etching and charge diffusion in charge accumulation layers.
Innovation Solution
The design features memory strings with inclined sidewalls of conductive and interlayer insulation layers, allowing for improved charge accumulation and reduced gate leakage, and separate formation of charge accumulation layers on each wordline conductive layer to enhance data retention and reduce erroneous write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods with vertical sidewalls are used, then the manufacturing process is simple, but gate leakage occurs due to damage during RIE and data retention deteriorates due to charge diffusion
Solution Approach 1:
The patent applies asymmetry by forming sidewalls of conductive layers and interlayer insulation layers with inclined surfaces rather than vertical surfaces. The sidewalls are designed to be inclined such that the distance from the central axis of the columnar semiconductor layer becomes larger at lower positions than at upper positions, creating an asymmetric structure that prevents charge diffusion while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies local quality by forming charge accumulation layers separately on each wordline conductive layer at specific local positions. This localized charge accumulation structure ensures that charges are confined to specific regions, preventing diffusion to adjacent memory cells and improving data retention characteristics
2Quantity of substance
If charge accumulation layers are formed covering all conductive layers, then charge accumulation capacity increases, but charges diffuse causing degradation of data retaining characteristics
Solution Approach 1:
The patent applies segmentation by dividing the charge accumulation structure into separate charge accumulation layers, each formed on a specific wordline conductive layer. This segmentation isolates charges in distinct regions, preventing diffusion between different memory cells while maintaining sufficient charge accumulation capacity for reliable data storage
3Productivity
If device dimensions are refined to increase storage capacity, then integration density improves, but cost increases due to EUV exposure devices and physical improvement limits are reached
Solution Approach 1:
The patent applies dimensionality change by transitioning from a conventional two-dimensional planar structure to a three-dimensional structure with columnar semiconductor layers extending in the vertical direction. This vertical integration approach increases storage capacity without requiring further refinement of horizontal device dimensions, thereby avoiding the need for expensive EUV exposure devices and associated manufacturing challenges
Data Source
AI summary
A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.