3D Gate Stack With Inclined Source Gate for Higher Turn-On Current
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Solution Overview
Problem
Current three-dimensional semiconductor devices face challenges in improving operational reliability due to limitations in the design of gate stack structures and manufacturing methods, which affect the performance and efficiency of source select transistors and memory cell transistors.
Innovation Solution
The semiconductor device incorporates a source contact structure with a gate stack structure having inclined source gate patterns and a channel pattern that penetrates the gate stack, along with a manufacturing method involving the formation of supports, multi-layered memory layers, and gap fill insulating layers to enhance the structural integrity and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate stack structures are used in three-dimensional semiconductor devices, then manufacturing simplicity is maintained, but operational reliability and turn-on current performance deteriorate
Solution Approach 1:
The gate stack structure is segmented into multiple functional regions: source gate patterns with inclined surfaces, channel patterns penetrating the gate stack, and drain gate patterns. This segmentation allows each region to be optimized independently for its specific function, improving overall operational reliability while managing complexity through modular design
Solution Approach 2:
Different regions of the gate stack are given different local qualities: the source gate pattern has an inclined surface facing the source contact structure to enhance turn-on current, the channel pattern provides vertical conduction paths, and the drain gate pattern has a different configuration. This local differentiation optimizes performance at each critical interface
2Power
If conventional source gate patterns are used, then manufacturing process simplicity is maintained, but turn-on current of source select transistors is insufficient
Solution Approach 1:
The source gate pattern incorporates an inclined surface (curved or angled geometry) facing the source contact structure, replacing conventional flat gate patterns. This curved/angled geometry enhances the electric field distribution and increases turn-on current while being manufacturable through standard lithography and etching processes
3Reliability
If simple channel structures are used, then device structure simplicity is maintained, but electrical characteristics and structural integrity deteriorate
Solution Approach 1:
The channel structure transitions from a planar two-dimensional configuration to a three-dimensional vertical structure that penetrates through the gate stack. This dimensional change enables all-around gate control of the channel, significantly improving electrical characteristics and structural integrity through enhanced electrostatic control
Data Source
AI summary
A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.