Indented Die Backside Structure for Flip-Chip BLR Reliability
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Solution Overview
Problem
Flip chip electronic devices face board level reliability (BLR) challenges due to thermal expansion coefficient (CTE) mismatches between silicon dies and underfill materials, leading to issues like solder joint cracking and inter-level dielectric cracking, which are exacerbated by the use of different molding compounds that increase manufacturing costs.
Innovation Solution
Incorporating indents into the backside of semiconductor dies, coupled with conductive terminals, to mitigate CTE mismatches by reducing plastic work density and enhancing board level reliability through controlled thermal expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different molding compound materials are used to mitigate CTE mismatching, then board level reliability is improved, but manufacturing cost increases and manufacturing difficulty increases
Solution Approach 1:
The patent applies local quality by creating an indent specifically at the die backside region where CTE mismatch stresses are most concentrated. This localized structural modification allows the use of standard molding compounds while achieving improved reliability, as the indent reduces plastic work density only where needed rather than requiring different materials throughout the entire package.
Solution Approach 2:
The patent changes the geometric parameter of the die backside by introducing an indent with specific depth and dimensions. This parameter change reduces the plastic work density in the critical region, thereby mitigating CTE mismatch effects without requiring different molding compound materials, thus avoiding increased manufacturing costs.
2Reliability
If different molding compound materials are used to mitigate CTE mismatching, then board level reliability is improved, but device complexity increases
Solution Approach 1:
The indent structure introduces local quality by modifying only the die backside region rather than changing the entire package structure or materials. This localized approach improves reliability while minimizing device complexity, as the rest of the device architecture remains unchanged.
Solution Approach 2:
The patent segments the die backside by creating a distinct indent region separated from the main die body. This segmentation allows the stress management function to be isolated to a specific area, simplifying the overall device design compared to using different molding compounds throughout.
3Reliability
If the die backside is modified with an indent, then plastic work density is reduced and reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent defines specific parameter ranges for the indent depth (e.g., 10-50 micrometers) to achieve the desired reduction in plastic work density while maintaining manufacturability. By establishing concrete parameter specifications, the patent balances manufacturing precision requirements with reliability improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The indents effectively reduce the risk of solder joint cracks and other reliability issues by up to 28%, thereby extending the board level reliability lifetime and improving thermal performance.
Implementation Method 1
Flip chip electronic devices can be susceptible to board level reliability (BLR) challenges caused by materials with different coefficients of thermal expansion (CTE). The CTE mismatch between a silicon die and an underfill material can induce potential underfill delamination and contribute to the BEOL damage.
Data Source
AI summary
An electronic device includes a substrate having conductive features, and a semiconductor die having conductive terminals along a first side, and an indent that extends into an opposite second side, the conductive terminals attached to respective ones of the conductive features of the substrate. A method of fabricating an electronic device includes forming an indent into a second side of a semiconductor die and attaching conductive terminals along an opposite first side of the semiconductor die to respective conductive features of a substrate.