Independent CSR Clocking for IP Block Power Reduction
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Solution Overview
Problem
Existing integrated circuit (IC) designs face issues with higher power dissipation, additional latency, and design complexity due to common clocking of IP blocks and configuration and status registers (CSRs), which also restrict software access and physical placement of retention power rails.
Innovation Solution
Implement independent clocking for CSRs using a derived clock rate that is an integer division slower than the IP block's clock rate, synchronized but independent, allowing software to access CSRs without activating the IP block, with minimal design area impact and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If common clock lines are routed to both IP block and CSRs, then CSRs operate at the same clock speed as IP blocks, but power dissipation increases
Solution Approach 1:
The patent segments the clocking system by providing separate clock signals for the IP block and CSRs. The IP block receives a first clock signal while CSRs receive a second clock signal with a lower frequency, allowing independent clocking and reducing power dissipation in CSRs when IP block is inactive.
Solution Approach 2:
The patent changes the clock frequency parameter for CSRs relative to the IP block. The CSR clock frequency is set to be lower than the IP block clock frequency, enabling power savings while maintaining functional operation of CSRs at their own optimized rate.
2Speed
If common clock lines are used for IP block and CSRs, then CSRs operate at the same clock speed, but latency in accessing CSRs increases
Solution Approach 1:
By segmenting the clock distribution, the patent allows CSRs to operate independently of IP block clocking, enabling faster access to CSRs without being constrained by IP block activation timing. The independent clocking removes the coupling that causes access latency.
3Speed
If common clock lines are used for IP block and CSRs, then CSRs operate at the same clock speed, but constraints on physical placement of retention power rails increase
Solution Approach 1:
The patent segments the clocking architecture to allow independent placement of retention power rails for CSRs. This independence removes the coupling between IP block clocking and CSR power delivery, freeing physical placement constraints and allowing flexible routing of retention power rails closer to CSR locations.
4Loss of energy
If custom CDC synchronizers are used for CSR clocking, then CSRs can operate on slower dedicated clock, but design effort increases
Solution Approach 1:
Instead of using complex custom CDC synchronizers, the patent segments the clock distribution by providing separate clock signals from the clock manager to the CSRs. This approach achieves independent clocking with simpler architecture, reducing design effort while maintaining power savings.
5Loss of energy
If custom CDC synchronizers are used for CSR clocking, then CSRs can operate on slower dedicated clock, but design area increases
Solution Approach 1:
The patent uses simple clock signal routing and gating from the clock manager to provide independent clocking to CSRs, avoiding the need for large custom CDC synchronizer circuits. This segmented approach achieves the same power savings with minimal area overhead.
6Loss of energy
If custom CDC synchronizers are used for CSR clocking, then CSRs can operate on slower dedicated clock, but power consumption increases
Solution Approach 1:
The patent segments the clocking system to provide independent low-frequency clock signals to CSRs, achieving power savings without requiring complex custom CDC synchronizers. The simple clock gating approach reduces design complexity while maintaining the power consumption benefits.
Data Source
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AI summary
This document describes systems and techniques that enable independent clocking for configuration and status registers (CSRs). The described systems and techniques can provide a clock signal to a CSR set of an IP block with a derived clock rate an integer division slower than a clock rate of another clock signal that enables operation of the IP block, which may include communication between the IP block and an application processor. The derived clock rate is synchronous to but independent of the clock rate of the clock signal. In this way, the application processor and other entities can access the CSR set independent of clocking of the IP block. For example, the application processor can read from or write to the CSR set without waking the IP block from an Auto Clock Gated mode. By so doing, described aspects of independent clocking can reduce power dissipation associated with the CSR set.