Indium Bump Stack with Thick Cu Pillar for Cryogenic Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flip chip interconnect structures for cryogenic electronic systems face challenges due to the brittleness of tin-based solders at deep cryogenic temperatures and the limitations of indium deposition methods, such as physical vapor deposition, which are slow and costly, and electroplating, which requires incompatible materials like nickel for room temperature use.
Innovation Solution
The development of an under bump metallization (UBM) stack with a thick copper conductive pillar and an indium superconducting solder bump, where the copper pillar's thickness prevents intermetallic region growth at room temperature, allowing for the use of indium as a ductile and superconducting material at cryogenic temperatures, and using a titanium tungsten or tungsten titanium adhesion and barrier layer with a thin copper seed layer for electroplating compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If physical vapor deposition is used to deposit indium, then indium solder bumps can be formed, but the process is slow and costly
Solution Approach 1:
The patent replaces the physical vapor deposition process with electroplating, substituting a mechanical/physical deposition method with an electrochemical process that is faster, more cost-effective, and scalable for mass production while maintaining indium bump formation quality
Solution Approach 2:
The patent changes the deposition method parameter from physical vapor deposition to electroplating, fundamentally altering the process mechanism to achieve both high productivity and manufacturing precision for indium solder bump formation
2Productivity
If electroplating is used to form indium bumps, then productivity and cost-effectiveness improve, but nickel material is required which is incompatible with cryogenic superconducting applications
Solution Approach 1:
The patent extracts and removes the nickel seed layer from the electroplating process, eliminating the harmful material that is incompatible with cryogenic superconducting applications, while retaining the benefits of electroplating for indium bump formation
Solution Approach 2:
The patent introduces alternative seed layer materials (TiW, WTi, Ru, Rh, or Ir) that serve as intermediaries between the substrate and indium electroplating, providing electroplating compatibility without introducing materials harmful to superconducting applications at cryogenic temperatures
3Reliability
If indium is used as solder material, then ductility and superconducting properties at cryogenic temperatures are achieved, but intermetallic region growth occurs at room temperature
Solution Approach 1:
The patent applies preliminary action by forming a diffusion barrier layer (Ru, Rh, or Ir) before depositing indium, which prevents intermetallic region growth at room temperature during fabrication and storage, while allowing indium to maintain its ductility and superconducting properties at cryogenic operating temperatures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures reliable mechanical and electrical integrity of the interconnect structure at cryogenic temperatures, preventing catastrophic failures and maintaining structural integrity through controlled intermetallic region growth, while allowing for scalable and cost-effective indium solder bump formation.
Implementation Method 1
a thick copper conductive pillar and an indium superconducting solder bump, where the copper pillar's thickness prevents intermetallic region growth at room temperature
Implementation Method 2
electroplating, which requires incompatible materials like nickel for room temperature use
Implementation Method 3
Indium also superconducts below 3.4K
Data Source
AI summary
A cryogenic under bump metallization (UBM) stack includes an adhesion and barrier layer and a conductive pillar on the adhesion and barrier layer. The conductive pillar functions as a solder wetting layer of the UBM stack and has a thickness. An indium superconducting solder bump is on the conductive pillar. The thickness of the conductive pillar is sufficient to prevent intermetallic regions, which form in the conductive pillar at room temperature due to interdiffusion, from extending through the entire thickness of the conductive pillar to maintain the structural integrity of the UBM stack. The indium (In) solder bump may be formed through electroplating, with the conductive pillar being copper (Cu) and the adhesion and barrier layer being titanium tungsten (TiW) and a thin seed layer of copper (Cu), or a layer of titanium (Ti).