Indium Bump Planarization for Wafer Hybridization
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Solution Overview
Problem
The integration of dissimilar materials in semiconductor fabrication is hindered by differences in thermal expansion coefficients and bowing or lack of flatness, which existing through silicon via (TSV) technology struggles to address effectively, especially when trying to achieve high-density interconnects on a wafer level.
Innovation Solution
A method involving the use of indium bump technology with thick dielectric layers to create a planar surface and accommodate thermal mismatches, where indium bumps are deposited and patterned in dielectric films to enable high-density interconnects between dissimilar materials, allowing for room temperature hybridization and preventing lateral shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If TSV technology is used to integrate dissimilar materials, then electrical interconnect density is improved, but manufacturing reliability deteriorates due to thermal expansion mismatch and wafer bowing
Solution Approach 1:
The patent introduces indium bumps as an intermediary material between dissimilar semiconductor wafers. Indium serves as a mediator that accommodates thermal expansion differences and wafer bowing through its ductility, enabling reliable hybridization at room temperature while maintaining high interconnect density
Solution Approach 2:
The patent changes the hybridization temperature parameter from high temperature (typical TSV process) to room temperature. This parameter change allows the use of indium bumps that can accommodate thermal expansion mismatches and wafer bowing without requiring thermal processing, thereby improving manufacturing reliability
2Measurement precision
If wafer hybridization is conducted at chip level, then alignment precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the hybridization process into two stages: first forming indium bumps on individual wafers at chip level for precise alignment, then performing wafer-level bonding. This segmentation allows alignment precision to be achieved during bump formation while the subsequent wafer-level process reduces overall manufacturing cost
3Ease of manufacture
If photoresist is used to pattern indium deposits, then manufacturing simplicity is improved, but manufacturing precision deteriorates due to photoresist damage to indium columns
Solution Approach 1:
The patent uses a dielectric layer as an intermediary mold to pattern indium deposits. The dielectric layer serves as a protective intermediary that defines the pattern without requiring photoresist to be in direct contact with the indium, thereby preventing photoresist damage while maintaining manufacturing simplicity
Solution Approach 2:
The patent performs preliminary patterning of the dielectric layer to create molds before depositing indium. This preliminary action establishes the pattern structure in advance, allowing indium to be deposited into pre-formed cavities without requiring photoresist to withstand the deposition process, thus preserving indium column uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable high-density interconnects between dissimilar materials at the wafer level, reducing fabrication costs and improving alignment, while accommodating thermal expansion mismatches and wafer bow, resulting in a more robust and efficient semiconductor device hybridization process.
Implementation Method 1
depositing indium or an alloy of indium in the holes; melting the indium or alloy of indium deposited in the holes to form indium columns that are uniform in size and shape
Implementation Method 2
The two wafers may, for example, utilize copper or aluminum stud bumps in thick dielectric to remove the bow and create a planar surface
Implementation Method 3
the ability to accommodate mismatches in the coefficients of thermal expansion of the constituent materials due to the ductility of indium and the ability to hybridize at room temperature
Implementation Method 4
when either the copper studs are driven into the indium bumps or when indium bumps are driven into other indium bumps during hybridization of two different materials
Data Source
AI summary
The disclosed technique may be used to electrically and physically connect semiconductor wafers. The wafer may utilize a thick dielectric. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together.