Inductively Peaked Clock Buffer for Low-Jitter 224 Gb/s Fanout
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Solution Overview
Problem
The challenge is to achieve high-speed, low-jitter clock distribution for 224 Gb/s transceivers while maintaining energy efficiency, as the increased clock frequency from 112 Gb/s to 224 Gb/s requires more power and improved jitter performance.
Innovation Solution
The solution involves using shunt-series and series-shunt inductive configurations in clock distribution stages to filter random jitter, cancel power supply induced deterministic jitter, and support higher fanout, thereby reducing power consumption and improving jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased from 112 Gb/s to 224 Gb/s, then data rate is improved, but power consumption increases and jitter performance deteriorates
Solution Approach 1:
The patent changes the topological parameters of the clock buffer by introducing series and shunt inductors to create an inductively-peaked configuration. This parameter change modifies the frequency response and impedance characteristics, enabling the buffer to operate efficiently at higher frequencies (28 GHz for 224 Gb/s) while maintaining lower power consumption and reduced jitter compared to conventional inverter-based buffers.
2Productivity
If clock frequency is increased from 112 Gb/s to 224 Gb/s, then data rate is improved, but jitter performance deteriorates
Solution Approach 1:
The patent modifies the clock buffer topology by adding inductors in series and shunt configurations, creating an inductively-peaked response that selectively amplifies the fundamental clock frequency while attenuating harmonics and noise. This parameter change in the circuit topology directly improves jitter performance at 28 GHz operation by filtering random jitter and reducing thermal noise, while maintaining the high data rate capability.
3Adaptability or versatility
If multiple multiplexers and demultiplexers are used for multi data-rate operation, then adaptability is improved, but clock quality deteriorates due to series switches lowering fanout and generating thermal noise
Solution Approach 1:
The patent introduces inductors as intermediary elements in the multiplexer and demultiplexer circuits. These inductors act as mediators that restore the fanout capability degraded by series switches and filter out thermal noise generated by the switching elements. The inductive peaking compensates for the harmful effects of the switches, allowing multiple data-rate operation with maintained clock quality and reduced random jitter.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed operation at 224 Gb/s with best-in-class jitter numbers and reduced power consumption, achieving excellent energy efficiency for the clock distribution.
Implementation Method 1
A first inductive clock buffer stage is provided. The first inductive clock buffer stage includes a first inductor and a first clock buffer circuitry having an input and an output. The input of the first clock buffer circuitry is coupled to the input of the first inductor and to an output of a voltage controlled oscillator. The output of the first clock buffer circuitry is coupled to the output of the first inductor.
Implementation Method 2
The second inductive clock buffer stage is adapted to cancel noise generated by a first inductive clock buffer stage, wherein the second inductive clock buffer stage includes a second inductor and a second clock buffer circuitry having an input and an output.
Data Source
AI summary
A clock buffer that uses low-to-medium quality factor (e.g., QF of 2 to 5) inductors in shunt-series and in series-shunt configuration in high-speed clock distribution stages. Shunt-series and series-shunt inductors extend amplifier bandwidth. Applying shunt-series and series-shunt inductors to high-speed clock distribution filters jitter, attenuates supply noise, and improves fanout. An asymmetric multiplexer with inductors in shunt or in shunt-series configurations. Another asymmetric multiplexer with capacitively coupled tri-stateable inverter-based buffer stages. These two multiplexer techniques along with the ability to ‘hide’ a load of a non-preferred path at a virtual ground node of the shunt inductor, the multiplexer improves the jitter and power consumption of the preferred path significantly. A de-multiplexer (DeMux) is also shown using inductors. A combination of a shunt-multiplexer and an inductor-based DeMux is also discussed.