Multi-layered Chip Inductor Asymmetric Margin Design
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Solution Overview
Problem
The demand for miniaturized multi-layered chip inductors has increased, but existing technologies face challenges in securing high capacity while preventing delamination due to large cutting margins.
Innovation Solution
A multi-layered chip electronic component is designed with a specific area ratio of the coil pattern to the overall body, where 0.40≦Ai:Ao≦1.03 and 0.13≦Ae:At, using magnetic layers and conductive patterns to form coil patterns, with a narrower margin in the width direction than in the length direction, and a size range of 2.0±0.1 mm by 1.6±0.1 mm, to optimize inductance and impedance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chip size is reduced for miniaturization, then the capacity is improved, but the cutting margin increases causing delamination
Solution Approach 1:
The patent applies asymmetry by creating unequal margin widths in different directions: the first margin width in the length direction is greater than the second margin width in the width direction. This asymmetric margin distribution allows the chip to be miniaturized while maintaining sufficient cutting margins in critical directions to prevent delamination during the cutting process.
Solution Approach 2:
The patent changes the parameters of margin widths to optimize both miniaturization and delamination prevention. By specifying that the length direction margin is greater than the width direction margin, and defining specific relationships between margin widths and chip dimensions, the patent achieves parameter optimization that simultaneously enables size reduction and maintains structural integrity during cutting.
2Quantity of substance
If the coil pattern area is increased to secure high inductance capacity, then the inductance is improved, but the available chip area for other functions is reduced
Solution Approach 1:
The patent utilizes the third dimension (depth/thickness) by forming coil patterns through stacked conductive layers connected by via holes. This multi-layer coil structure increases the effective inductance capacity without proportionally increasing the planar area occupation, thereby resolving the contradiction between inductance capacity and available chip area.
Solution Approach 2:
The patent implements nesting by placing via holes within the coil pattern area and embedding multiple conductive layers within each other. The coil patterns are formed by stacking conductive patterns on different layers and connecting them through via holes, creating a nested structure that maximizes inductance within the constrained chip area.
3Quantity of substance
If the margin width is reduced to increase coil pattern area, then the inductance capacity is improved, but the structural integrity during cutting is reduced
Solution Approach 1:
The patent applies asymmetry by creating unequal margin widths in different directions: the first margin width in the length direction is greater than the second margin width in the width direction. This asymmetric margin distribution allows the chip to be miniaturized while maintaining sufficient cutting margins in critical directions to prevent delamination during the cutting process.
Solution Approach 2:
The patent applies local quality by providing different margin widths in different directions based on local requirements. The length direction margin is optimized for preventing delamination during cutting, while the width direction margin is minimized to maximize coil pattern area. This localized optimization of margin widths resolves the contradiction between structural integrity and inductance capacity.
Data Source
AI summary
There is provided a multi-layered chip electronic component including: a multi-layered body formed by stacking a plurality of magnetic layers; and conductive patterns disposed between the plurality of magnetic layers and electrically connected in a lamination direction to form coil patterns, wherein in a case in which a single coil pattern in the coil pattern is projected in the length and width directions of the multi-layered body, when an area of the magnetic layer inside of the coil pattern is defined as Ai and an area of the magnetic layer outside of the coil pattern is defined as Ao, 0.40≦Ai:Ao≦1.03 is satisfied.