InFO Package Stress Management via Protective Coating
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Solution Overview
Problem
Integrated Fan Out (InFO) package technology faces challenges due to stresses from wafer fabrication processes, such as warpage and thermal cycling, which cause defects like micro-cracking in molding compounds and redistribution layers, leading to lower production yields, increased costs, and longer production times.
Innovation Solution
A protective PM coating is applied to integrate heterogeneous dies within a molding compound to prevent cracking, and a redistribution structure is formed over the PM coating, providing rigidity and preventing damage during fabrication. This approach includes forming an interconnect structure on a core substrate and attaching it to the redistribution structure, with more routing within the redistribution structure to improve electrical performance and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wafer fabrication processes (backside grinding, CMP, annealing) are performed to improve manufacturing precision and device performance, then device functionality and integration density are improved, but stresses (wafer warpage, thermal cycling) cause micro-cracking in molding compounds and redistribution layers, reducing reliability and production yield
Solution Approach 1:
A protective coating is applied to the backside of the substrate before wafer fabrication processes to preemptively protect against stress-induced cracking. This preliminary protective measure prevents damage before it occurs during subsequent manufacturing steps like backside grinding, CMP, and annealing.
Solution Approach 2:
The protective coating acts as a cushioning layer that absorbs and distributes stresses generated during wafer fabrication processes. This beforehand cushioning prevents stress concentration that would otherwise cause micro-cracking in the molding compound and redistribution layers, thereby maintaining high production yields.
2Reliability
If a protective coating is applied to prevent cracking and improve reliability, then production yield and manufacturing reliability are improved, but additional process steps are required, potentially increasing production time and complexity
Solution Approach 1:
The protective coating is applied as a uniform layer across the entire backside of the substrate, providing consistent protection without requiring complex patterned structures. This homogeneous approach simplifies the process compared to more complex protective schemes while maintaining high reliability.
Solution Approach 2:
The protective coating modifies the mechanical and thermal parameters of the substrate system, changing its stress distribution characteristics. This parameter change enables the substrate to withstand fabrication processes better, improving yield without requiring fundamentally new process steps.
3Productivity
If more routing is placed within the redistribution structure to improve electrical performance, then electrical performance and functional density are improved, but the structure becomes more complex and manufacturing becomes more difficult
Solution Approach 1:
The patent utilizes multiple layers and three-dimensional routing paths within the redistribution structure to achieve high functional density. By moving from two-dimensional to three-dimensional routing, electrical performance is improved without proportionally increasing manufacturing complexity, as the additional dimension provides more routing options.
Solution Approach 2:
The redistribution structure is divided into multiple segments or layers, each handling specific routing functions. This segmentation allows complex electrical routing to be broken down into manageable manufacturing steps, improving electrical performance while keeping manufacturing feasible through systematic division of the routing task.
Data Source
AI summary
Integrated fan-out devices, wafer level packages, and methods of manufacturing the same are described herein. Die-attach pads and leveling film are used to attach a plurality of heterogeneous semiconductor dies to a substrate to align external contacts of the semiconductor dies at a first level. The leveling film may also be used during deposition of an encapsulant to at least partially fill a gap between the semiconductor dies. Once the leveling film is removed, a protection layer is formed over the semiconductor dies and within a recess of the encapsulant left behind by the leveling film during encapsulation. A redistribution layer and external connectors are formed over the protection layer to form the InFO device and an interposer may be attached to the redistribution layer to form the wafer level package.