InFO-POP TIV Cavity Structure for High-Density I/O Packaging

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Solution Overview

Problem

The increasing miniaturization of semiconductor chips and the need for higher I/O pad density in semiconductor dies complicates packaging, leading to issues such as limited I/O pad numbers due to pitch limitations and potential solder bridges in conventional fan-in packages, and the inefficiency of packaging sawed dies, which can result in wasted resources on defective dies.

Innovation Solution

The development of Integrated Fan-Out (InFO) packages that utilize through-vias and redistribution layers to increase I/O pad density, allowing for fan-out packages and efficient use of known-good-dies, with processes involving sacrificial polymer dots, metal seed layers, and redistribution lines to form uniform metal posts and recesses, enabling efficient packaging and connection to package components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fan-in packaging is used with smaller die sizes, then throughput is improved and cost is reduced, but the number of I/O pads is limited due to pitch limitations and solder bridges may occur

Engineering Contradiction:
ImprovethroughputVSAvoidnumber of I/O pads
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent transitions from planar fan-in packaging to three-dimensional fan-out packaging using through-vias. The I/O pads are redistributed from the original die surface to the package substrate surface through vertical through-vias, effectively adding a vertical dimension to the I/O pad layout. This allows I/O pads to be packed at higher density on the package substrate while maintaining adequate pitch, resolving the contradiction between throughput improvement and I/O pad quantity limitation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If pitch of I/O pads is decreased to increase density, then I/O pad density is improved, but solder bridges may occur

Engineering Contradiction:
ImproveI/O pad densityVSAvoidsolder bridge risk
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The invention redistributes I/O pads from the horizontal plane of the die to the horizontal plane of the package substrate through vertical through-vias. This dimensional transformation allows achieving high I/O pad density on the package substrate without reducing the pitch on the die itself, thereby maintaining solder joint reliability while increasing overall I/O capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Through-vias act as intermediaries that transfer electrical connections from the die I/O pads to the package substrate I/O pads. This intermediary structure allows the die to maintain its original pad pitch for reliable soldering, while the package substrate provides a larger area for high-density I/O pad arrangement, effectively decoupling the pitch requirements of the die and the package.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If dies are sawed before packaging to form fan-out packages, then I/O pad redistribution to greater area is enabled, but cost and effort are wasted on defective dies

Engineering Contradiction:
ImproveI/O pad redistribution areaVSAvoidwaste on defective dies
Core Design Contradiction:
Quantity of substanceVSLoss of substance

Solution Approach 1:

The patent performs packaging on complete wafers before singulation, allowing defective dies to be identified and discarded after singulation. This preliminary packaging action enables the use of fan-out technology to redistribute I/O pads to a greater area on the package substrate, while maintaining the ability to eliminate defective units after they are separated from the wafer, thus avoiding waste on defective dies.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12588523B2InFO-POP structures with TIVs having cavities
Publication Date: 2026.03.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12588523B2 patent drawing
  • US12588523B2 patent drawing
  • US12588523B2 patent drawing

AI summary

A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.