Injection-Locked Reference Path for Low-Phase-Noise Clock Multiplication
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Solution Overview
Problem
Existing clock signal generation methods for frequency synthesizers often result in output signals with high phase noise, which can affect the quality of the generated frequencies, particularly in communication devices where precise frequency control is crucial.
Innovation Solution
A reference path circuit incorporating an injection locked multiplier (ILM) and a group of buffer amplifiers is used to generate a sinusoidal output clock signal, where the ILM receives a sinusoidal reference signal and produces an output signal at an integer multiple of the reference frequency within its locking range, and the buffer amplifiers further process this signal to reduce phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock signal generation methods are used, then the frequency synthesizer can generate output signals, but the output signals exhibit high phase noise which degrades signal quality
Solution Approach 1:
An injection-locked multiplier (ILM) is introduced as an intermediary component between the reference clock source and the frequency synthesizer. The ILM receives a reference clock signal and generates a frequency-multiplied clock signal with reduced phase noise, thereby mediating the clock signal generation process to eliminate harmful phase noise while maintaining frequency multiplication functionality
Solution Approach 2:
The invention changes the operational parameters of the clock signal generation by using an injection-locked multiplier that operates at a different frequency multiplication factor than traditional dividers. By adjusting the injection locking parameters and utilizing the ILM's inherent frequency multiplication capability, the system achieves optimal phase noise reduction while maintaining the required clock frequency for the frequency synthesizer
2Speed
If frequency multiplication is performed to generate higher frequency clock signals, then the clock frequency requirement is met, but phase noise increases which affects output signal quality
Solution Approach 1:
The injection-locked multiplier serves as a mediator that performs frequency multiplication in a controlled manner. Unlike traditional frequency dividers that inherently increase phase noise when multiplying frequency, the ILM uses injection locking mechanism to generate the multiplied frequency while maintaining low phase noise characteristics, thus resolving the contradiction between achieving high clock frequency and minimizing phase noise
Solution Approach 2:
The invention replaces conventional frequency division/multiplication circuitry with an injection-locked multiplier that operates on different principles. The ILM uses resonant oscillation and injection locking phenomena to achieve frequency multiplication, substituting the traditional mechanical/electronic division approach with a resonance-based approach that inherently provides better phase noise performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly reduces phase noise in the output clock signal, enhancing the quality and stability of the generated frequencies, thereby improving the performance of frequency synthesizers in communication devices.
Implementation Method 1
an injection locked multiplier (ILM) may be arranged to receive, from a reference oscillator, an input sinusoidal reference signal at a reference frequency and generate, for input to a first buffer amplifier in the group, an output sinusoidal signal at an output frequency that is based on an integer multiple of the reference frequency
Data Source
AI summary
Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.