Inline 2D Convolution Hardware Engine for Networking Devices
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Solution Overview
Problem
Existing solutions for performing 2D convolution and CNN computations in networking devices rely on software execution on general-purpose CPUs or GPUs, which are inefficient in terms of performance and power consumption, and are not designed for inline processing within networking devices.
Innovation Solution
A 2D convolution hardware engine is embedded within a networking device to perform inline and in-memory 2D convolution operations, eliminating the need for external memory buffering and reducing latency. This engine is integrated into the data path of the networking device and can be configured through programmable registers to support various parameters and operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software execution on general-purpose CPU or GPU is used, then flexibility and programmability are maintained, but performance and power consumption are inefficient
Solution Approach 1:
The patent replaces the mechanical/software-based execution model (CPU/GPU executing software code) with a dedicated hardware engine that performs 2D convolution operations directly in hardware. This substitution eliminates the overhead of software interpretation and enables parallel processing at the hardware level, significantly improving performance while reducing power consumption compared to general-purpose processors.
Solution Approach 2:
The hardware engine is designed to be self-sufficient by integrating both computation units and memory structures within the same device. The engine can perform convolution operations using its own internal resources without requiring external memory buffering or data transfer, enabling autonomous operation that reduces latency and power consumption.
2Loss of time
If external memory buffering is used, then data storage capacity is sufficient, but latency and complexity increase
Solution Approach 1:
The patent merges the computation engine and memory structures into a single integrated unit. The hardware engine contains internal memory resources that are directly coupled to the processing units, eliminating the need for separate external memory buffers. This integration allows data to be processed immediately upon arrival without intermediate buffering stages, reducing latency while simplifying the overall system architecture.
Solution Approach 2:
The hardware engine is pre-configured with the necessary computational resources and memory structures to handle convolution operations immediately upon data receipt. The engine maintains ready-state computation units and internal buffers that are pre-allocated, allowing processing to begin without waiting for external memory allocation or data transfer setup, thus reducing processing latency.
3Productivity
If dedicated hardware engine is implemented, then processing speed and efficiency are improved, but device complexity increases
Solution Approach 1:
The hardware engine is divided into distinct functional modules including computation units, memory structures, and control logic. Each module performs a specific function within the convolution pipeline, allowing for independent optimization and maintenance. This segmentation enables the complex processing task to be distributed across multiple specialized units, achieving line-rate computation while managing complexity through modular design.
4Device complexity
If in-memory processing is implemented, then external memory buffering is eliminated, but internal memory requirements increase
Solution Approach 1:
The patent transitions from external memory buffering to internal memory integration by changing the spatial dimension of memory placement. Instead of using separate external memory devices, the memory structures are embedded within the same chip or processing unit, effectively moving memory from an external dimension to an internal dimension. This approach eliminates the need for complex buffering structures while keeping internal memory volume manageable through efficient memory hierarchy design.
Data Source
AI summary
A two-dimensional (2D) convolution hardware engine for a networking device includes processing circuitry that further includes multiple processing stages forming a pipeline to perform an inline and in-memory 2D convolution operation on a received dataset. A first processing stage of the pipeline shifts the dataset in a first direction of a 2D space, a second processing stage shifts the dataset in a second direction of the 2D space, a third processing stage calculates a product of each pixel of a kernel of the shifted 2D image by multiplying the pixel with a filter weight of the kernel, and a fourth processing stage calculates a sum of the products of all pixels of the kernel of the shifted 2D image. A convolutional neural network (CNN) computation hardware engine for performing an inline and in-memory CNN computation operation on the received dataset is included.