Semiconductor Air Spacer Layout for GAA Gate Capacitance Control
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Solution Overview
Problem
The integration of gate-all-around (GAA) devices in semiconductor manufacturing is challenging due to the complexity of fabricating features around the nanowire channel, which affects gate control and increases parasitic capacitance.
Innovation Solution
The introduction of air spacers sealed by inner spacers and source/drain features reduces parasitic capacitance by forming a semiconductor structure with alternating semiconductor layers and using etching processes to create notches and recesses, allowing for better balance in reducing capacitance while maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used for GAA devices, then manufacturing process compatibility is maintained, but parasitic capacitance increases and gate control deteriorates
Solution Approach 1:
The patent extracts the harmful dielectric material between the gate electrode and source/drain regions by forming air spacers through selective etching. This removal of the dielectric layer eliminates the parasitic capacitance pathway while maintaining the structural framework needed for device operation.
Solution Approach 2:
The patent changes the physical state of the spacer material from solid dielectric to gaseous air by removing the dielectric layer and forming air spacers. This parameter change from material presence to material absence directly reduces parasitic capacitance while maintaining mechanical support through the air spacer structure.
2Strength
If dielectric spacers are used between gate and source/drain, then structural support is provided, but parasitic capacitance is maintained
Solution Approach 1:
The air spacer acts as an intermediary structure that provides mechanical support and defines the geometric relationship between gate and source/drain regions without maintaining electrical capacitance. The air spacer mediates between the need for structural support and the need to eliminate parasitic capacitance.
Solution Approach 2:
The patent removes the dielectric material that would otherwise provide structural support, replacing it with an air spacer formed by selective etching. This extraction eliminates the parasitic capacitance while the air spacer maintains the necessary structural framework.
3Object-generated harmful factors
If air spacers are formed by removing dielectric material, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary patterning of the air spacer structure before final device assembly. By pre-forming the air spacer geometry through selective etching of sacrificial layers, the subsequent device fabrication steps are simplified and the overall manufacturing complexity is managed.
Solution Approach 2:
The air spacer structure is formed through self-aligned processes where the etching patterns automatically define the correct positions and dimensions. This self-service approach reduces the need for additional alignment steps and manual intervention, managing manufacturing complexity despite the added process step.
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes alternatingly stacked first semiconductor layers and second semiconductor layers. The method also includes laterally recessing the first semiconductor layers of the fin structure to form a plurality of notches, forming a plurality of inner spacers in the notches, laterally recessing the inner spacers to form a plurality of recesses in the inner spacers, and growing a source/drain feature over the fin structure. The recesses are sealed by the source/drain feature and the inner spacers to form a plurality of air spacers.