Inner Spacer Structure for Lower Capacitance Nanosheet FETs
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing low-cost, high-performance, and low-power integrated circuits (ICs) due to increased complexity in the semiconductor manufacturing process as a result of scaling down IC dimensions.
Innovation Solution
The method involves increasing the lateral thickness of inner spacers and forming them to extend past the end of channel regions into the source/drain regions, which can include low-K dielectric cores or air gaps within the inner spacers to reduce effective capacitance and improve AC gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacers are formed with conventional dimensions and structure, then manufacturing process remains simple, but AC gain is insufficient and effective capacitance is high
Solution Approach 1:
The patent implements a nested structure where a core is placed inside the inner spacer, creating a multi-layered configuration. The inner spacer has a first portion and a second portion with a core positioned between them, forming a nested arrangement that increases AC gain by 110-120% while managing effective capacitance through the layered structure.
Solution Approach 2:
The patent applies local quality by creating different portions of the inner spacer with distinct characteristics. The first portion and second portion have different geometries and positions relative to the channel region, with the second portion extending further laterally. This localized differentiation optimizes electrical properties in specific regions to enhance overall device performance.
2Reliability
If inner spacers extend further laterally into source/drain regions, then AC gain increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses a sacrificial layer positioned beneath the channel region that is removed in a preliminary step to create a cavity. This preliminary action defines the space where the inner spacer will later be formed, ensuring precise lateral extension into the source/drain regions without requiring direct precision control during spacer formation itself.
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary element that temporarily occupies the space where the inner spacer will eventually reside. This mediator allows for indirect formation of the inner spacer with controlled lateral extension, as the sacrificial layer's removal creates the necessary cavity while the spacer material conformally coats the remaining structures.
Data Source
AI summary
Provided are devices and methods for forming devices. An exemplary method includes etching a cavity in a vertical direction into a fin structure including at least one semiconductor nanosheet overlying a sacrificial layer, wherein the cavity is formed with a sidewall; recessing the sacrificial layer by a lateral distance to a recessed surface; forming an inner spacer laterally adjacent to the recessed surface of the sacrificial layer, wherein the inner spacer has a lateral width greater than the lateral distance; and growing epitaxial material in the cavity to form a source/drain region laterally adjacent to the inner spacer.