Inner Spacer Structures for Low-Capacitance GAA Transistors
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Solution Overview
Problem
The scaling down of semiconductor devices increases complexity and parasitic capacitance between source/drain regions and gate structures, negatively impacting device performance.
Innovation Solution
Incorporation of inner spacer structures between source/drain regions and gate structures using low-k dielectric materials to reduce parasitic capacitance, along with passivation layers to improve surface quality and reduce dangling bond vacancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then storage capacity and processing speed are improved, but parasitic capacitance between source/drain regions and gate structures increases
Solution Approach 1:
The patent introduces an inner spacer structure as an intermediary element positioned between the source/drain regions and the gate structure. This inner spacer acts as a mediator that physically separates and electrically isolates the source/drain regions from the gate, thereby reducing parasitic capacitance while allowing the device to maintain scaled dimensions for high productivity
Solution Approach 2:
The patent extracts the harmful capacitive coupling effect by removing the direct contact or close proximity between source/drain regions and gate structure through the inner spacer. This extraction of the harmful interaction allows the device to achieve both small dimensions and low parasitic capacitance
2Quantity of substance
If device dimensions are scaled down to increase storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent segments the device structure by introducing the inner spacer as a distinct component between source/drain regions and gate structure. This segmentation allows each element to be optimized independently while maintaining overall compactness, thereby increasing storage capacity without proportionally increasing manufacturing complexity
Solution Approach 2:
The inner spacer structure is nested within the overall device architecture, fitting into the space between existing components. This nesting approach allows the device to maintain compact dimensions for high storage capacity while using established manufacturing processes, thereby limiting the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces parasitic capacitance by 20% to 60% and increases drive currents by 20% to 50%, enhancing FET device performance.
Implementation Method 1
reduces parasitic capacitance by 20% to 60%
Data Source
AI summary
The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions.