Inorganic Inter-Die Gap Fill Structure for Low-Stress Multi-Chip Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current IC die disintegration techniques face challenges such as high cost, lower insertion efficiency, and increased z-height due to mechanical reliability issues caused by inter-die fill materials like epoxy-based mold materials, which introduce stress in multi-die structures as their thickness is reduced.
Innovation Solution
The use of multi-layered inorganic dielectric fill structures in composite IC die structures, where IC dies are bonded to a host substrate with inorganic gap filling material layers, allowing for efficient fill thickness comparable to the IC dies, and employing etch and deposition cycles to modify sidewall slopes and achieve global planarization, reducing stress and improving mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If epoxy-based mold material is used for inter-die fill, then the fill material is easy to manufacture and apply, but it introduces high stress that causes mechanical reliability problems as multi-die structure thickness is reduced
Solution Approach 1:
The patent changes the material parameter from organic epoxy-based mold material to inorganic dielectric material, fundamentally altering the stress characteristics and thermal expansion properties to resolve the mechanical reliability issue while maintaining manufacturability through established semiconductor fabrication processes
Solution Approach 2:
The patent uses composite inorganic dielectric material structures that combine multiple layers with different properties to achieve both mechanical reliability and ease of manufacture, leveraging the advantages of inorganic materials while maintaining process compatibility
2Reliability
If inorganic dielectric fill material is used, then mechanical reliability and stress reduction are improved, but the fabrication process complexity increases due to etch and deposition cycles
Solution Approach 1:
The patent segments the fill material deposition into multiple thin inorganic dielectric layers, each deposited and etched separately, which allows for better stress control and mechanical reliability while using standard semiconductor fabrication processes that are already complex but well-established
Solution Approach 2:
The patent transitions from a single-layer organic fill approach to a multi-layer inorganic structure, adding the dimension of layering to control stress distribution and improve mechanical reliability, with each layer contributing to the overall structural integrity
3Manufacturing precision
If multi-layered inorganic dielectric fill structures are used with etch and deposition cycles, then sidewall slope modification and global planarization are achieved, but manufacturing steps and time increase
Solution Approach 1:
The patent employs periodic cycles of deposition and etching to build up the inorganic dielectric layers with controlled sidewall slopes, using rhythmic alternating actions to achieve precise geometric control while maintaining efficient use of fabrication equipment
Solution Approach 2:
The patent performs preliminary deposition of inorganic dielectric material before final planarization, allowing sidewall slope modification to be achieved in advance, which streamlines the overall manufacturing process by preparing the structure for subsequent steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances mechanical reliability and reduces stress in multi-die structures, improving insertion efficiency and reducing costs by using inorganic materials that match the coefficient of thermal expansion of IC dies, leading to more stable and efficient composite IC die structures.
Implementation Method 1
a first layer of inorganic material is deposited within a space between adjacent IC dies
Implementation Method 2
depositing a first layer of inorganic material within a space between adjacent IC dies
Implementation Method 3
employing etch and deposition cycles to modify sidewall slopes
Data Source
AI summary
Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.