Input Buffer With Branched DFE Reset for High-Speed Memory Timing

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Solution Overview

Problem

As memory device speeds increase, the timing for resetting Decision Feedback Equalizers (DFEs) becomes more difficult due to propagation delays, potentially causing data loss if the DFE reset propagates before the output clock pulse, especially in high-speed implementations.

Innovation Solution

A branched DFE reset path is introduced to separate data and tap paths, allowing the DFE reset to start sooner while maintaining data integrity by independently resetting tap data without affecting the data path, loosening timing constraints and providing more output clock hold time margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the DFE reset propagates through the input buffer at high speeds, then the DFE can be reset in time for accurate data interpretation, but the data in the input buffer may be reset before being output causing data loss

Engineering Contradiction:

ImproveDFE reset timing accuracyVSAvoiddata loss

Core Design Contradiction:

ReliabilityVSLoss of information

Solution Approach 1:

The patent segments the DFE reset path into two separate paths: a first path for resetting DFE taps and a second path for resetting input buffer data. This segmentation allows each path to be controlled independently with appropriate timing, preventing the data loss that occurs when a single unified reset path is used at high speeds.

Inventive Principle:

Principle #1Segmentation

2Productivity

If additional buffering is included to meet higher clock speed demands, then productivity increases, but propagation delays grow making DFE reset timing more difficult

Engineering Contradiction:

Improveclock speedVSAvoidpropagation delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

By segmenting the reset path into separate tap reset and data reset paths, the patent eliminates the cumulative propagation delay problem. Each segmented path can be optimized independently, allowing additional buffering to be added for higher clock speeds without causing timing issues in the critical DFE reset path.

Inventive Principle:

Principle #1Segmentation

3Reliability

If the DFE reset is delayed to compensate for input buffer delays, then data integrity is maintained, but the DFE reset occurs too late for accurate interpretation

Engineering Contradiction:

Improvedata integrityVSAvoidDFE reset timing

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The segmented reset paths allow the tap reset to occur early without delay compensation (maintaining timing accuracy) while the data reset path maintains data integrity through separate control. This resolves the contradiction by eliminating the need to choose between early reset timing and data integrity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12505875B2Data input buffer with a branched DFE reset path

Publication Date: 2025.12.23 MICRON TECHNOLOGY INC

AI summary

Systems and methods are provided for a memory device that includes a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to reset taps of a DFE. The memory device also includes an input buffer. The input buffer includes a data branch configured to output data from the input buffer for use downstream in the memory device. The input buffer also includes a DFE reset branch configured to reset the taps for the DFE based on the DFE reset signal. Moreover, resetting the taps using the DFE reset branch does not reset output data of the data branch.