Input Buffer Clock Synchronization for Glitch-Free DRAM Writes
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Solution Overview
Problem
In semiconductor memory devices, particularly DRAM, the data input buffer enable signal often glitches and becomes inactive prematurely when multiple write commands are received in quick succession, disrupting data receipt due to improper synchronization, which existing timing adjustments cannot perfectly resolve.
Innovation Solution
Implementing a clock synchronization mechanism where the data input buffer enable signal is kept active if the gap between commands is less than a predetermined clock period, using a command shifter with flip-flops synchronized to a clock signal, ensuring the signal remains active through a synchronized data buffer enable signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If timing adjustments are made to extend buffer enable signal duration, then the buffer remains active longer, but the signal still glitches when multiple commands are received in quick succession
Solution Approach 1:
The patent implements dynamic timing adjustment where the buffer enable signal duration is adaptively extended based on the arrival pattern of multiple commands. When commands are received in quick succession, the signal duration is dynamically increased to prevent premature deactivation, resolving the contradiction between maintaining signal duration and ensuring signal stability.
Solution Approach 2:
The patent uses preliminary detection of command arrival patterns to pre-extend the buffer enable signal duration before glitches occur. By monitoring command timing in advance and proactively adjusting the signal duration, the system prevents signal instability rather than reacting to it after it occurs.
2Reliability
If the buffer enable signal is kept active for extended periods, then data receipt is maintained, but command timing precision may be compromised
Solution Approach 1:
The patent segments the buffer enable signal control into multiple independently controllable signals, each associated with specific command types or timing windows. This segmentation allows precise control over signal duration for different command scenarios, maintaining both data receipt continuity and command timing precision through differentiated signal management.
Data Source
AI summary
Apparatuses, systems, and methods for input buffer enable clock synchronization. A command shifter receives a command, such as a write command. The command shifter passes the command through latches of the shifter in synchronization with a clock signal. Data buffer enable logic provides a data buffer enable signal with a level based on how long it takes the command to pass through the command shifter. The data buffer enable logic synchronizes changes to the level of the data buffer enable signal to the clock signal.