Input Circuit Voltage Stabilization for Multi-Supply Level Shifters
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Solution Overview
Problem
The operational stability of semiconductor devices is compromised when multiple power voltages are used, leading to instability due to varying voltage sequences, which affects the performance and efficiency of memory systems.
Innovation Solution
An input circuit is designed with a buffer circuit driven by a first power voltage, a level shifter circuit driven by a second power voltage, and a voltage stabilization circuit that maintains the input node voltage of the level shifter at a specific level, ensuring stable operation regardless of the sequence of rising power voltages by using inverters and an NMOS transistor to control the ground voltage supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple power voltages are used to improve operational performance and power efficiency, then the operational stability of the semiconductor device deteriorates due to varying voltage sequences
Solution Approach 1:
The voltage stabilization circuit proactively monitors the voltage levels of both power voltages and preemptively activates the NMOS transistor to clamp the input node voltage when the second power voltage rises before the first power voltage, preventing the instability condition from occurring in the first place
Solution Approach 2:
The voltage stabilization circuit acts as an intermediary between the buffer circuit and level shifter circuit, isolating the level shifter from voltage fluctuations by clamping the input node voltage through the NMOS transistor when needed, thus mediating the interaction between the two circuits during unstable voltage transitions
Data Source
AI summary
An input circuit includes: a buffer circuit coupled to a pad, the buffer circuit being driven by a first power voltage; a level shifter circuit coupled to an output terminal of the buffer circuit, the level shifter circuit being driven by a second power voltage; and a voltage stabilization circuit coupled to an input node of the level shifter circuit, the voltage stabilization circuit being driven by the first power voltage and the second power voltage. The voltage stabilization circuit maintains a voltage of the input node of the level shifter circuit equal to or less than a given level sufficient to keep an output signal of the level shifter circuit at a specific logic value, when a voltage level of the second power voltage is rising and a voltage level of the first power voltage is kept at a low level.