Input Stage Body Impedance Circuit for Higher ESD Tolerance
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Solution Overview
Problem
Conventional input stage circuits in integrated circuits have weak electrostatic discharge (ESD) tolerance due to thinner gate gaps in advanced processes, leading to a trade-off between ESD tolerance and performance.
Innovation Solution
The integration of an impedance circuit between the body of the input transistor and a reference voltage in the input stage circuit, which isolates substrate noise during normal operation and prevents ESD charges from entering the transistor body during an ESD event.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an additional ESD protection resistor or secondary ESD protection circuit is added in the signal path to improve ESD tolerance, then ESD tolerance is improved, but signal input performance is reduced
Solution Approach 1:
An impedance circuit is introduced as an intermediary component between the body of the input transistor and the substrate. This impedance circuit acts as a mediator that blocks ESD charges from reaching the transistor body while maintaining proper transistor operation during normal signaling conditions, thus protecting the transistor without degrading signal performance
Solution Approach 2:
The solution applies a localized protection mechanism by connecting the impedance circuit specifically to the body terminal of the input transistor, rather than adding series resistors in the signal path. This localized approach targets the vulnerable body terminal directly, providing ESD protection where needed while leaving the signal path unchanged
2Manufacturing precision
If the gate gap of the transistor is made thinner to improve manufacturing precision in advanced processes, then manufacturing precision is improved, but ESD tolerance is reduced
Solution Approach 1:
The impedance circuit is configured to provide protective isolation between the substrate and the transistor body before ESD charges can cause damage. This pre-configured protective barrier cushions the vulnerable thin-gate transistor against incoming ESD charges, allowing the transistor to operate with thin gate gaps for improved manufacturing precision while maintaining ESD tolerance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively improves the ESD tolerance of the input stage circuit without compromising normal operating performance, while also enhancing common-mode rejection ratio (CMRR) and reducing substrate noise.
Implementation Method 1
the impedance circuit isolates a substrate noise
Implementation Method 2
When an ESD event occurs, the impedance circuit prevents ESD charges from the substrate from entering the body of the first input transistor
Data Source
AI summary
An integrated circuit including a signal connection pad, an electrostatic discharge (ESD) protection circuit, and an input stage circuit is provided. The ESD protection circuit is coupled to the signal connection pad. An input terminal of the input stage circuit is coupled to the ESD protection circuit. The input stage circuit includes a load circuit, a current source circuit, an input transistor, and an impedance circuit. A control terminal of the input transistor is coupled to the ESD protection circuit. A first terminal of the input transistor is coupled to the load circuit. A second terminal of the input transistor is coupled to the current source circuit. A first terminal of the impedance circuit is coupled to a body of the input transistor. A second terminal of the impedance circuit is coupled to a first voltage.