Inside-Core Event Trigger Debugging Control System

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Solution Overview

Problem

Conventional debugging methods for integrated circuits lack flexibility in selecting trigger signals and observing internal states, leading to increased debugging time and inefficiency, as they rely on fixed comparator signals and limited observability of internal core states.

Innovation Solution

A debugging control system that uses inside-core events as trigger conditions, incorporating a clock controller, debug control module, and graphical interface software to select and modify trigger signals and states, allowing for flexible combination of logical relations and sequencing of trigger events, and enabling the core to resume original program execution from a paused state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If fixed comparator and finite-state machine with pre-defined signals are used to detect trigger events, then trigger event detection accuracy is improved, but trigger event flexibility deteriorates

Engineering Contradiction:
Improvetrigger event detection accuracyVSAvoidtrigger event flexibility
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent transforms the fixed, static comparator into a dynamic, reconfigurable structure. The event comparator uses multiplexers and programmable logic to dynamically select and configure comparison signals at runtime, allowing the same hardware to adapt to different trigger event requirements without losing detection precision.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the parameters of the comparator by making it programmable. Instead of fixed comparison values and signals, the system allows dynamic modification of comparison parameters through programmable logic arrays and multiplexer configurations, enabling flexible trigger event definition while maintaining accurate detection.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If debug and trace hardware with pre-defined signals is used, then system complexity is reduced, but debugging capability deteriorates

Engineering Contradiction:
Improvedebug and trace architecture complexityVSAvoiddebugging capability
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The event comparator is designed to serve multiple debugging functions through a single unified structure. It can compare different types of signals (internal core signals, external signals, scan chain signals) and support various comparison modes (equality, inequality, pattern matching), replacing multiple specialized components with one multi-functional unit.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces an event comparator as an intermediary component between the debug control logic and the core signals. This mediator provides a flexible interface that translates diverse debugging requirements into unified comparison operations, simplifying the overall debug architecture while enhancing capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of information

If scan-based debugging method is used to read out core states, then observability of internal states is improved, but debugging time increases

Engineering Contradiction:
Improveobservability of internal statesVSAvoiddebugging time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-configuring the event comparator with trigger conditions and pre-loading the event buffer with comparison data. When a trigger event occurs, the system is already prepared to immediately capture and record the relevant state information, eliminating the need for time-consuming sequential scan operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention enables skipping through the traditional slow scan-based observation process by using the event comparator to directly detect and capture trigger events in real-time. The system rushes through the debugging process by immediately recording state information when triggers occur, rather than methodically scanning through all flip-flops.

Inventive Principle:
Principle #21Skipping (Rushing through)

4Manufacturing precision

If trigger signals are predetermined before manufacturing, then manufacturing precision is improved, but signal reconfigurability deteriorates

Engineering Contradiction:
Improvetrigger signal definition precisionVSAvoidsignal reconfigurability
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent makes the trigger signal configuration dynamic rather than static. The event comparator uses programmable logic arrays and multiplexers that can be configured at manufacturing time but can also be reprogrammed in the field, allowing the system to adapt to different debugging needs while maintaining precise signal definitions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention allows parameter changes in trigger signal definitions through programmable logic. The same hardware can be configured with different comparison parameters, signal sources, and logic conditions, enabling reconfigurability without sacrificing the precision of signal definitions during manufacturing.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8892973B2Debugging control system using inside core event as trigger condition and method of the same
Publication Date: 2014.11.18 NAT CHENG KUNG UNIV
  • US8892973B2 patent drawing
  • US8892973B2 patent drawing
  • US8892973B2 patent drawing

AI summary

A debugging control system using inside-core events as trigger conditions and a method of the same are revealed. The method includes following steps. First set up at least one trigger condition and a search range of the clock cycle according to internal states of a core under debug. Pause clock and recover clock of each clock cycle within the search range. Retrieve data of scan chains of the core under debug by a shift buffer during the clock pausing. Next combine data of the scan chains by a trigger comparator circuit to form trigger signals and check whether the trigger signals satisfy the trigger condition. If the trigger condition is satisfied or the trigger signal is over the search range, the clock is paused continuingly and internal states of the scan chains of the core under debug are output otherwise the core under debug is recovered.