Instant-Lock ADPLL Using Initial Phase Compensation
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Solution Overview
Problem
Existing PLLs face a trade-off between bandwidth requirements and other performance metrics, with low-bandwidth PLLs having higher locking times, which negatively impact data throughput and power consumption.
Innovation Solution
Implementing an all-digital phase-locked loop (ADPLL) circuit with a one-shot or instant lock mechanism that sets initial conditions for building blocks to achieve near-zero settling-time by calibrating and compensating for phase differences, allowing rapid phase and frequency lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low bandwidth is used to suppress noise, then phase noise performance is improved, but locking time increases
Solution Approach 1:
The patent applies preliminary action by pre-calibrating the phase detector offset and pre-setting the charge pump current before the PLL locking process. This preparation eliminates the need for the PLL to spend time adjusting these parameters during locking, thereby reducing locking time without requiring increased bandwidth that would amplify phase noise.
2Loss of time
If high bandwidth is used to reduce locking time, then locking speed is improved, but phase noise increases
Solution Approach 1:
By performing offset calibration and parameter optimization before the locking process, the system achieves fast locking response without needing high bandwidth. The preliminary setup ensures that the PLL starts from an optimized state, allowing low bandwidth to effectively suppress phase noise while still achieving rapid locking through the head-start provided by pre-calibration.
3Measurement precision
If traditional PLL calibration is performed continuously, then accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by performing calibration only at power-up or when frequency changes occur, rather than continuously. This selective calibration approach maintains measurement precision when needed while dramatically reducing power consumption by keeping the calibration circuit inactive during normal operation.
Solution Approach 2:
The system uses self-service by automatically calibrating the phase detector offset using its own internal resources (charge pump, loop filter, and feedback path) without requiring external calibration equipment or continuous power-intensive correction mechanisms. The one-shot calibration at startup provides sufficient accuracy for extended operation.
4Object-affected harmful factors
If analog PLL components are used, then phase noise performance is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies mechanics substitution by replacing complex analog calibration circuits with a simplified digital control approach. The offset calibration is performed using digitally controllable current sources and switches that are easier to implement and consume less power than traditional analog calibration mechanisms, while achieving the same phase noise suppression performance.
Data Source
AI summary
Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.