Multi-Phase Clock Generator With Instant-On Delay-Mixer Architecture

The patent applies preliminary action by pre-configuring the delay elements and phase mixers in a fixed architectural structure that requires no dynamic adjustment during initialization. The delay values are determined at design time through the interconnection structure rather than requiring runtime convergence, enabling instant-on capability where clock outputs are generated within one input clock cycle.

The patent extracts and removes the power-consuming control circuits that are present in conventional designs. Instead of using controllable delay lines or analog cells with control logic, the invention uses a fixed architectural structure where delay is achieved through the inherent propagation delay of the interconnection structure and logic elements, eliminating the need for power-hungry control mechanisms while maintaining multiple phase generation capability.

The patent segments the frequency control function into discrete, fixed delay elements rather than using continuous voltage-controlled adjustment. The system divides the clock period into multiple fixed delay stages, each contributing a predetermined amount of delay. This segmentation allows frequency adjustment through selecting different combinations of delay elements while maintaining instant-on capability, as no voltage ramping or convergence is required.