Instruction Sequence Triggering via Shared Condition Monitoring

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Solution Overview

Problem

In triggered instruction architectures (TIAs), the need to monitor multiple condition-dependent instructions limits the number of instructions that can be stored and processed efficiently, leading to increased complexity and power consumption due to the requirement of separately specified trigger conditions for each instruction.

Innovation Solution

Implementing a mechanism where a sequence of instructions can be triggered in response to a single condition specified by a sequence-start instruction, reducing the need for separate condition monitoring of subsequent instructions and allowing them to be stored with fewer bits, thereby decreasing power consumption and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple condition-dependent instructions are monitored separately, then each instruction can be triggered accurately, but the number of instructions that can be stored and processed is limited

Engineering Contradiction:
Improvenumber of instructions stored and processedVSAvoidcomplexity of condition monitoring
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the trigger conditions of multiple sequential instructions into a single shared condition. When this common condition is met, a sequence of instructions is triggered together, eliminating the need to monitor and evaluate separate conditions for each instruction in the sequence. This combining approach directly increases the number of instructions that can be stored and processed while reducing monitoring complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal trigger condition that serves multiple instructions simultaneously. A single condition evaluation can trigger multiple instructions in sequence, making the condition-monitoring mechanism multi-functional. This universal approach allows the system to handle more instructions without proportionally increasing the complexity of condition monitoring logic.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate trigger conditions are specified for each instruction, then each instruction can be precisely controlled, but power consumption increases

Engineering Contradiction:
Improveprecision of instruction triggeringVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple separate trigger condition evaluations into a single shared condition check. By evaluating one common condition instead of multiple separate conditions, the power consumption of the condition monitoring logic is significantly reduced while still ensuring precise control over when the instruction sequence executes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies partial action by having instructions in the sequence share a common trigger condition rather than each having full independent conditions. This partial specification of conditions is sufficient for precise control while avoiding the excessive power consumption that would result from fully independent condition monitoring for each instruction.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of operation

If each instruction specifies its own conditions, then instruction execution can be precisely controlled, but the number of bits required to store instructions increases

Engineering Contradiction:
Improvecontrol of instruction executionVSAvoidnumber of bits to store instructions
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent merges the condition specifications of multiple instructions into a single shared condition definition. Instead of storing separate condition fields for each instruction in the sequence, the system stores one common condition that applies to all instructions, significantly reducing the total number of bits required while maintaining precise execution control.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal condition specification that serves multiple instructions. This single condition definition is reused across multiple instructions in the sequence, making the instruction representation more compact. The universal condition maintains full control precision while reducing the quantity of stored data.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11977896B2Issuing a sequence of instructions including a condition-dependent instruction
Publication Date: 2024.05.07 ARM LTD
  • US11977896B2 patent drawing
  • US11977896B2 patent drawing
  • US11977896B2 patent drawing

AI summary

An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.