Insulated Die With Conformal Parylene Layer
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Solution Overview
Problem
Conventional semiconductor chip packages face challenges in achieving precise electrical insulation, particularly in terms of dimensions and process stability, leading to issues with creep currents and reliability due to insufficient insulating properties of adhesive materials.
Innovation Solution
A semiconductor chip with a significant portion of its surface covered by a thin, conformally applied electrically insulating layer, such as parylene, providing robust and reliable dielectric isolation, which can be efficiently manufactured and processed to prevent creep currents and mechanical damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional adhesive materials are used for electrical insulation, then the chip can be mounted on a mounting base, but the insulating properties are insufficient leading to creep currents and reliability issues
Solution Approach 1:
The patent replaces conventional mechanical adhesive bonding with a thin-film dielectric layer deposited directly onto the chip surface. This substitution transitions from a mechanical assembly approach to a integrated thin-film technology, achieving superior electrical insulation properties and eliminating creep current issues that plague adhesive-based solutions.
Solution Approach 2:
The patent changes the insulation approach from thick adhesive layers (hundreds of micrometers) to thin-film dielectric layers (nanometer to micrometer scale). This parameter change in thickness and material properties dramatically improves disruptive strength and eliminates creep current pathways while maintaining electrical insulation functionality.
2Reliability
If a thin electrically insulating layer is applied onto the semiconductor chip surface, then disruptive strength and creep current suppression are significantly improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent merges the electrical insulation function with the chip fabrication process itself by depositing dielectric layers during standard semiconductor manufacturing steps. This integration combines multiple functions into a unified process flow, avoiding the need for separate insulation assembly steps and reducing overall manufacturing complexity despite the advanced materials used.
Solution Approach 2:
The thin-film dielectric layer is deposited directly onto the chip surface using standard semiconductor fabrication techniques, allowing the chip to self-insulate without requiring external assembly operations. The chip structure itself provides the insulation, eliminating the need for separate adhesive bonding processes and reducing manufacturing steps.
3Manufacturing precision
If conventional bulk encapsulant is used, then the chip is protected during processing, but precise adjustment of insulating properties and dimensions is difficult
Solution Approach 1:
The patent replaces bulk encapsulant materials with thin-film dielectric layers deposited using precise semiconductor fabrication techniques. This substitution enables atomic-level control over layer thickness and composition, achieving manufacturing precision of nanometer scale compared to the millimeter-scale variability inherent in bulk material processing.
Solution Approach 2:
The patent transitions from thick bulk encapsulant materials (millimeter scale) to thin-film dielectric layers (micrometer and nanometer scale). This parameter change enables precise control over insulation dimensions through deposition process parameters such as film thickness, composition, and crystalline structure, achieving superior dimensional control and process stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses creep currents and enhances disruptive strength, ensuring reliable electrical insulation and protection against voltage-induced degradation, while allowing for precise control and efficient manufacturing processes.
Implementation Method 1
an electrically insulating layer surrounding (in particular covering, more particularly covering in direct contact with semiconductor material of the semiconductor chip) at least part (in particular at least 60%, more particularly at least 90%, of an external surface) of the semiconductor chip
Data Source
AI summary
An insulated chip comprising a semiconductor chip comprising at least one chip pad and an electrically insulating layer surrounding at least part of the semiconductor chip.