Insulating Layer for Fine Pitch Flip-Chip Electrical Isolation
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Solution Overview
Problem
In fine pitch flipchip applications, the existing solder mask dam limits the bump and signal trace pitch, leading to potential bridging or shorting issues between adjacent interconnect structures during the solder reflow process, which affects the reliability and robustness of solder joints between the flipchip and printed circuit board.
Innovation Solution
The formation of an insulating layer over the conductive traces, which maintains electrical isolation from bumps even if they extend over signal traces during reflow, eliminating the need for a solder mask dam and allowing for a finer pitch between interconnect structures without causing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a solder mask dam is used to prevent bridging between bumps and signal traces, then electrical isolation is improved, but the pitch between interconnect structures increases and device density decreases
Solution Approach 1:
The patent removes the solder mask dam from the interconnect structure, extracting the problematic element that was forcing larger pitch spacing. Instead of using a solder mask dam, the invention forms an insulating layer directly over the signal trace, eliminating the need for lateral spacing between bumps and adjacent traces while maintaining electrical isolation.
Solution Approach 2:
The patent transitions from preventing bridging through lateral spacing (horizontal dimension) to preventing bridging through vertical insulation. By forming an insulating layer over the signal trace in the vertical dimension, the invention eliminates the need for increased lateral pitch spacing, allowing finer pitch between interconnect structures.
2Manufacturing precision
If lateral spacing is increased to prevent bridging during reflow, then manufacturing defects are reduced, but interconnect density decreases
Solution Approach 1:
The patent applies preliminary action by forming the insulating layer over the signal trace before the bump reflow process. This pre-established insulation ensures that even if bumps extend over signal traces during reflow, electrical isolation is already in place, preventing bridging defects without requiring increased lateral spacing.
Solution Approach 2:
The insulating layer acts as an intermediary element between the bump and the signal trace. This intermediate insulating material prevents direct electrical contact (bridging) between the conductive bump and conductive signal trace, enabling fine pitch interconnects without compromising manufacturing precision.
3Productivity
If solder mask dam is removed to enable finer pitch, then interconnect density improves, but electrical isolation reliability deteriorates
Solution Approach 1:
The patent changes the parameter of electrical isolation from relying on lateral spacing (distance) to relying on material property (insulating layer). By changing the isolation mechanism from geometric separation to material-based separation, the invention enables finer pitch while maintaining or improving electrical isolation reliability.
Data Source
AI summary
A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around bumps between the semiconductor die and substrate.