Integrated Capacitor Grid Plates High Specific Capacitance
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Solution Overview
Problem
Integrated capacitors in ICs face challenges in achieving high capacitance per unit area, low loss, and low self-inductance, particularly in high-frequency applications, while also requiring effective noise shielding and compatibility with standard CMOS fabrication sequences.
Innovation Solution
The design employs 'cabled' conductive structures, such as horizontal and vertical filaments or columns, surrounded by conductive grids or curtains, interconnected with vias to provide high specific capacitance and noise shielding, using existing CMOS process sequences and techniques like damascene and dual damascene for forming conductive layers and vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple conductive strips are used to increase capacitance, then capacitance per unit area is improved, but device complexity increases
Solution Approach 1:
The capacitor structure is divided into multiple conductive strips arranged in parallel within each node, with alternating polarity. This segmentation allows the capacitor to achieve higher capacitance per unit area by utilizing multiple discrete conductive elements rather than a single large plate, while the regular alternating pattern maintains manufacturing simplicity.
Solution Approach 2:
Conductive strips from different metal layers are vertically aligned and electrically connected through vias to form nested three-dimensional structures. This nesting approach increases the effective capacitance volume without proportionally increasing the planar footprint, as upper-layer strips are positioned within the horizontal footprint of lower-layer strips.
2Stability of the object's composition
If conductive strips are offset alternately to balance substrate coupling, then coupling balance is improved, but surface area consumption increases
Solution Approach 1:
The invention intentionally creates asymmetric offset patterns where conductive strips in alternating layers are shifted relative to each other. Specifically, odd-numbered layers are offset in one direction while even-numbered layers are offset in the opposite direction, creating an asymmetric but balanced overall structure that controls substrate coupling while minimizing area consumption.
Solution Approach 2:
The patent transitions from two-dimensional planar capacitor designs to three-dimensional vertically-stacked structures. By utilizing the vertical dimension with multiple metal layers and vias, the design achieves balanced substrate coupling through vertical offset patterns without requiring proportional increases in horizontal surface area.
3Object-affected harmful factors
If thick silicon dioxide layer is used to reduce substrate coupling, then coupling reduction is improved, but manufacturing difficulty increases
Solution Approach 1:
The invention extracts the substrate coupling problem from the solution space by using offset patterns that naturally reduce coupling through geometric arrangement rather than relying on thick dielectric layers. The alternating offset pattern of conductive strips creates effective electrical isolation from the substrate without requiring additional thick oxide deposition steps.
Solution Approach 2:
The patent changes the geometric parameters of the capacitor structure by introducing vertical offsets between layers and alternating offset directions. These parameter changes in the spatial arrangement of conductive strips provide substrate coupling control through structure geometry rather than through material parameter changes like increasing dielectric thickness.
4Area of stationary object
If overlapping conductive strips connected to the same node are used, then surface area efficiency is improved, but inter-layer capacitance decreases
Solution Approach 1:
The invention applies different spatial arrangements to different nodes of the capacitor. Conductive strips connected to the same node are overlapped in the horizontal plane to maximize area efficiency, while conductive strips connected to opposite nodes are offset to create the capacitive coupling interface. This local differentiation of spatial quality optimizes both area efficiency and capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves high specific capacitance with effective noise shielding, improving high-frequency performance and compatibility with standard IC fabrication processes, enhancing self-resonant frequency and quality of capacitor circuits.
Implementation Method 1
Capacitors are used in IC systems for a variety of purposes. In many instances, it is desirable to incorporate (integrate) a capacitor in the IC chip. A simple approach is to form two conductive plates with an intervening dielectric
Implementation Method 2
A simple approach is to form two conductive plates with an intervening dielectric; however, this consumes a relatively large area for the capacitance obtained
Implementation Method 3
integrated capacitors have high capacitance per unit area, low loss (resistance), and low self-inductance, which improves highfrequency applications by increasing self-resonant frequency and the quality of capacitor circuits
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
A capacitor (200) in an integrated circuit ("IC") has a distribution grid (226) formed in a first patterned metal layer of the integrated circuit and a first vertical conductive filament (202) connected to and extending away from the distribution grid along a first direction. A second vertical conductive filament (203) is connected to the distribution grid and extends in the opposite direction. First (225) and second grid plates (224) are formed in the metal layers above and below the first patterned metal layer. The grid plates surround the first and second vertical conductive filaments. The distribution grid, first vertical conductive filament and second vertical conductive filament are connected to and form a portion of a first node of the capacitor and the first grid plate and the second grid plate are connected to and form a portion of a second node of the capacitor.