Integrated Multilayer Chip Capacitor Module Reducing ESL
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Solution Overview
Problem
Multilayer chip capacitors face challenges in reducing power network impedance across both high and low frequency regions due to limited mounting area, as increasing the number of capacitors in parallel increases mounting area and affects impedance at different frequencies.
Innovation Solution
An integrated multilayer chip capacitor module with multilayer chip capacitors arranged close to each other and connected via conductive adhesive material, allowing for higher density mounting and reduced ESL, thereby increasing capacitance and decreasing impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a greater number of capacitors are connected in parallel to reduce power network impedance, then impedance reduction is improved, but mounting area increases
Solution Approach 1:
Multiple multilayer chip capacitors are integrated into a single module structure where they are mounted close to one another on a common substrate. The external electrodes of adjacent capacitors are electrically connected through conductive adhesive material, merging multiple capacitor functions into one compact assembly that reduces overall mounting area while maintaining low impedance performance.
Solution Approach 2:
The capacitors are arranged in a nested configuration where multiple capacitors are positioned in close proximity on a shared substrate structure. This nesting approach allows maximum capacitor density within the module footprint, enabling more capacitors to be integrated without proportionally increasing the overall mounting area.
2Reliability
If multi-terminal multilayer chip capacitors are used to reduce ESL and increase mounting density, then high frequency decoupling is improved, but manufacturing complexity increases
Solution Approach 1:
The capacitor module is segmented into multiple independent multilayer chip capacitor units, each with its own terminal structure optimized for low ESL. This segmentation allows each capacitor to be manufactured using standard low-ESL designs while the overall module achieves high mounting density through the systematic arrangement of these segmented units on a common substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables better decoupling effects across a broader frequency range by reducing total impedance in both high and low frequency regions, allowing for more stable power circuits in micro-processor units.
Implementation Method 1
external electrodes on adjacent sides of adjacent ones of the multilayer chip capacitors in the capacitor support are electrically connected to each other by a conductive adhesive material
Data Source
AI summary
An integrated multilayer chip capacitor module including: plurality of multilayer chip capacitors arranged close to one another and co-planar with one another; and a capacitor support accommodating the multilayer chip capacitors, wherein each of the multilayer chip capacitors includes a rectangular parallelepiped capacitor body and a plurality of first and second external electrodes formed on at least two sides of the capacitor body, and the external electrodes on adjacent sides of adjacent ones of the multilayer chip capacitor in the capacitor support are electrically connected to each other by a conductive adhesive material.